Module Definition
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Module : rstmgr_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_src 100.00 100.00 100.00
tb.dut.u_sys_src 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_src

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_pd_n[0].u_pd_rst 100.00 100.00 100.00
gen_rst_pd_n[0].u_rst_pd_mux 100.00 100.00 100.00 100.00
u_aon_rst 100.00 100.00 100.00
u_rst_aon_mux 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sys_src

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rst_pd_n[0].u_pd_rst 100.00 100.00 100.00
gen_rst_pd_n[0].u_rst_pd_mux 100.00 100.00 100.00 100.00
u_aon_rst 100.00 100.00 100.00
u_rst_aon_mux 100.00 100.00 100.00 100.00

Line Coverage for Module : rstmgr_ctrl
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_ctrl.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
52 1 1


Cond Coverage for Module : rstmgr_ctrl
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)])
             ----1----   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_lc_src
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_ctrl.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
52 1 1


Cond Coverage for Instance : tb.dut.u_lc_src
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)])
             ----1----   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_sys_src
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_ctrl.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
52 1 1


Cond Coverage for Instance : tb.dut.u_sys_src
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)])
             ----1----   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%