SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_src | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_sys_src | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_rst_pd_n[0].u_pd_rst | 100.00 | 100.00 | 100.00 | ||||
gen_rst_pd_n[0].u_rst_pd_mux | 100.00 | 100.00 | 100.00 | 100.00 | |||
u_aon_rst | 100.00 | 100.00 | 100.00 | ||||
u_rst_aon_mux | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_rst_pd_n[0].u_pd_rst | 100.00 | 100.00 | 100.00 | ||||
gen_rst_pd_n[0].u_rst_pd_mux | 100.00 | 100.00 | 100.00 | 100.00 | |||
u_aon_rst | 100.00 | 100.00 | 100.00 | ||||
u_rst_aon_mux | 100.00 | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
47 | 1 | 1 | |
52 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 59 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)]) ----1---- ------------------2------------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
47 | 1 | 1 | |
52 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 59 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)]) ----1---- ------------------2------------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
47 | 1 | 1 | |
52 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 59 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)]) ----1---- ------------------2------------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |