RV_DM Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.230s	1.128ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.180s	167.975us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	0.890s	145.109us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	4.330s	2.740ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	0.850s	84.800us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	9.480s	2.731ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	5.190s	1.595ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.806m	33.956ms	5	5	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	47.570s	24.841ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	5.900s	8.208ms	1	2	50.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	3.590s	3.664ms	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.400s	268.680us	1	2	50.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.740s	325.986us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.110s	127.158us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.060s	539.763us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.740s	45.650us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.320s	702.257us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.160s	124.690us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.690s	13.031us	0	2	0.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	0.720s	60.634us	1	2	50.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.400s	268.680us	1	2	50.00
V1	rom_read_access	rv_dm_rom_read_access	0.830s	23.108us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.230s	57.835us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.280s	764.120us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.227m	7.380ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.062m	1.097ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	11.020s	4.464ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.062m	1.097ms	5	5	100.00
		rv_dm_csr_rw	2.280s	764.120us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.680s	127.517us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.720s	154.602us	5	5	100.00
V1		TOTAL			156	161	96.89
V2	idcode	rv_dm_smoke	1.230s	1.128ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.500s	298.047us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.780s	43.107us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	0.850s	72.407us	1	2	50.00
V2	sba	rv_dm_sba_tl_access	45.070s	14.391ms	19	20	95.00
		rv_dm_delayed_resp_sba_tl_access	25.990s	14.303ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	2.248m	50.000ms	18	20	90.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.971m	43.948ms	10	20	50.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.680s	15.594us	0	2	0.00
V2	sba_debug_disabled	sba_debug_disabled			0	0	--
V2	ndmreset_req	rv_dm_ndmreset_req	1.140s	205.307us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	0.930s	166.451us	4	5	80.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	3.820s	1.132ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	46.260s	13.878ms	11	40	27.50
V2	stress_all	rv_dm_stress_all	21.580s	6.768ms	11	50	22.00
V2	alert_test	rv_dm_alert_test	0.780s	50.813us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.560s	1.065ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.560s	1.065ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.062m	1.097ms	5	5	100.00
		rv_dm_csr_hw_reset	2.230s	57.835us	5	5	100.00
		rv_dm_csr_rw	2.280s	764.120us	20	20	100.00
		rv_dm_same_csr_outstanding	8.320s	1.601ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.062m	1.097ms	5	5	100.00
		rv_dm_csr_hw_reset	2.230s	57.835us	5	5	100.00
		rv_dm_csr_rw	2.280s	764.120us	20	20	100.00
		rv_dm_same_csr_outstanding	8.320s	1.601ms	20	20	100.00
V2		TOTAL			191	276	69.20
V2S	tl_intg_err	rv_dm_sec_cm	1.450s	352.128us	5	5	100.00
		rv_dm_tl_intg_err	20.360s	4.010ms	20	20	100.00
V2S	sec_cm_bus_integrity	sec_cm_bus_integrity			0	0	--
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sec_cm_lc_hw_debug_en_intersig_mubi			0	0	--
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	33.530s	4.418ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			372	512	72.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	24	85.71
V2	18	16	8	44.44
V2S	10	2	2	20.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
80.51	94.44	80.05	87.69	78.21	83.66	98.42	41.11

Failure Buckets

UVM_ERROR (jtag_dmi_monitor.sv:105) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 58 failures:
- Test rv_dm_cmderr_busy has 1 failures.
  - 0.rv_dm_cmderr_busy.69156853055723289040721199569538939054504621492850688420184368189392174370910
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest/run.log
```
  UVM_ERROR @  76354959 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @  76354959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_cmderr_exception has 1 failures.
  - 1.rv_dm_cmderr_exception.13101284273549469241797858422637395137260931504088427882286387144850626565857
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest/run.log
```
  UVM_ERROR @ 365811405 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 365811405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_hart_unavail has 1 failures.
  - 1.rv_dm_hart_unavail.81366116778055570634360659821742068641722610099106750123363057080830220656804
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest/run.log
```
  UVM_ERROR @  22199867 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @  22199867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_jtag_dmi_dm_inactive has 1 failures.
  - 1.rv_dm_jtag_dmi_dm_inactive.39164577060785870795765523546544753068331798928015267109668436670730267324209
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest/run.log
```
  UVM_ERROR @ 120352031 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 120352031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
  - 1.rv_dm_jtag_dmi_debug_disabled.18070196093414925210145231681673378431609560511047658493681962352375265541854
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
```
  UVM_ERROR @  16704922 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @  16704922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
- Test rv_dm_autoincr_sba_tl_access has 9 failures.
  - 0.rv_dm_autoincr_sba_tl_access.81681717449926089142449334272154593621233737118993787883877901093674910953718
    Line 503, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_dm_autoincr_sba_tl_access.2276960286594170214884875579564581786026921340929713548606330629299756164904
    Line 335, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
- Test rv_dm_bad_sba_tl_access has 1 failures.
  - 6.rv_dm_bad_sba_tl_access.74722420631548865098223490685181831992191166117192386068966972214288635694995
    Line 323, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 8 failures:
- Test rv_dm_tap_fsm_rand_reset has 8 failures.
  - 0.rv_dm_tap_fsm_rand_reset.9835100487975327042818142100443800675730493619424935499194961188105355318104
    Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 1738183039 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1738183039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rv_dm_tap_fsm_rand_reset.5326535988160992956306575234362611270649682006210697030233955972165661781324
    Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 3147260931 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3147260931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 7 failures:

Test rv_dm_tap_fsm_rand_reset has 7 failures.

2.rv_dm_tap_fsm_rand_reset.94009298112031181851758783486948833519785478598025671830274980786547882683518
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 4298338496 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4298338496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.rv_dm_tap_fsm_rand_reset.3594902118844312954253358950965723491676000997799888406560671879059904181543
Line 377, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 20936259826 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 20936259826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 6 failures:

Test rv_dm_jtag_dmi_debug_disabled has 1 failures.

0.rv_dm_jtag_dmi_debug_disabled.31155983496443014929250402615373744324745355693199818158332700337557610832249
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log

  UVM_ERROR @  15593598 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 673419338 [0x2823904a])
  UVM_INFO @  15593598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all has 3 failures.

17.rv_dm_stress_all.38890262541998134467134847457325519807150090545826269885215904856115902180732
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log

  UVM_ERROR @  54670727 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 1923262892 [0x72a2a9ac])
  UVM_INFO @  54670727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.rv_dm_stress_all.43928977787749586246640748324862352055502728414651511241291940850674290768248
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 899384822 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3503746414 [0xd0d6ed6e])
  UVM_INFO @ 899384822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rv_dm_stress_all_with_rand_reset has 2 failures.

30.rv_dm_stress_all_with_rand_reset.96516247834815998483970008351899105075402530654030164194810035387024952468639
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 121251778 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (754331867 [0x2cf630db] vs 1896755270 [0x710e3046])
  UVM_INFO @ 121251778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.rv_dm_stress_all_with_rand_reset.39853373639279771848507543774227763916797474466407227286417615958313575373691
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 907270814 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 2866965244 [0xaae26afc])
  UVM_INFO @ 907270814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 6 failures:
- Test rv_dm_tap_fsm_rand_reset has 6 failures.
  - 4.rv_dm_tap_fsm_rand_reset.94326503936762215532618974422784224684763240059728665510910898647932940121520
    Line 396, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 34629278074 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 34629278074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.rv_dm_tap_fsm_rand_reset.27899172995740291342465664470932020185307498614693349179709130488635341078714
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 288444514 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 288444514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 4 failures:

Test rv_dm_stress_all has 4 failures.

1.rv_dm_stress_all.11285305653171656561459761218061064746043051200135520306069471875232571351941
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log

  UVM_ERROR @  40703183 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
  UVM_INFO @  40703183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rv_dm_stress_all.97424702443355829443264206048090672305930931185521865679252097138762715049353
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 248645284 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (27815871398 [0x679f483a6] vs 4209 [0x1071])
  UVM_INFO @ 248645284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol has 4 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 2.rv_dm_stress_all_with_rand_reset.109411457569945581510053689597474452940517371789366147609899518319453203160822
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  14084951 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
  UVM_INFO @  14084951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.rv_dm_stress_all_with_rand_reset.74983871559194708068727268201594464108617377774773016181863975573887725338261
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  29262551 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
  UVM_INFO @  29262551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test rv_dm_stress_all has 1 failures.
  - 49.rv_dm_stress_all.110460535316209339708729762467327463545909142594509306090745521260603344920083
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @   5000329 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
  UVM_INFO @   5000329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 4 failures:
- Test rv_dm_stress_all_with_rand_reset has 4 failures.
  - 5.rv_dm_stress_all_with_rand_reset.113573509374824183943942363110662427555733644770878921146831800171962944104593
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 870915819 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
  UVM_INFO @ 870915819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.rv_dm_stress_all_with_rand_reset.84828058513937646956658315372750467003564338529227929661762074384825988248311
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1278986994 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
  UVM_INFO @ 1278986994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 4 failures:
- Test rv_dm_tap_fsm_rand_reset has 4 failures.
  - 11.rv_dm_tap_fsm_rand_reset.21631205935815673053743520307114300562634320066840832148462990359135335014440
    Line 409, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 13878055522 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
  UVM_INFO @ 13878055522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rv_dm_tap_fsm_rand_reset.5869072680915367274459605996854551093772480835400233409209981780033242209827
    Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 3924862787 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
  UVM_INFO @ 3924862787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 17.rv_dm_stress_all_with_rand_reset.52711492975897945784147673148719512339683628124327990991005919535179463472858
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1249113030 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 1249113030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.rv_dm_stress_all_with_rand_reset.60202551427086588685129461143116594716253333488024781571049373788772457539336
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/45.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6762452076 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 6762452076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed Error-[NOA] Null object access has 2 failures:
- Test rv_dm_abstractcmd_status has 2 failures.
  - 0.rv_dm_abstractcmd_status.80798328326936671352831453535074187173354537146378882215790385691265100695466
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
  - 1.rv_dm_abstractcmd_status.93131724811249690441721874449968752915854899402019715863429515928207649454746
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```

UVM_ERROR (jtag_dmi_monitor.sv:48) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * } has 2 failures:

Test rv_dm_progbuf_read_write_execute has 1 failures.

0.rv_dm_progbuf_read_write_execute.67138709954586636055487496594924343130444717409485693326437791491970263498898
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest/run.log

  UVM_ERROR @   3432691 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0  dr_len: 'h0  ir: 'h0  dr: 'hxxxxxxxxxxxxxxxx  dout: 'hxxxxxxxxxxxxxxxx  bus_op: BusOpWrite  skip_reselected_ir: 'h0  ir_pause_count: 'h0  dr_pause_count: 'h0  }
  . ir_len & dr_len are both zero, or non-zero.
  UVM_INFO @   3432691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_sba_tl_access has 1 failures.

11.rv_dm_sba_tl_access.100979480979185059910652003532469579824622776369607686154248297654385504690988
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest/run.log

  UVM_ERROR @   4444232 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0  dr_len: 'h0  ir: 'h0  dr: 'hxxxxxxxxxxxxxxxx  dout: 'hxxxxxxxxxxxxxxxx  bus_op: BusOpWrite  skip_reselected_ir: 'h0  ir_pause_count: 'h0  dr_pause_count: 'h0  }
  . ir_len & dr_len are both zero, or non-zero.
  UVM_INFO @   4444232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 2 failures:
- Test rv_dm_tap_fsm_rand_reset has 2 failures.
  - 1.rv_dm_tap_fsm_rand_reset.96393039975534737932789418483413110857116662375516609225404817737734887507402
    Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 1719040128 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1719040128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rv_dm_tap_fsm_rand_reset.16591292136264956149543084995961363156532762212255769267320307752903738491741
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 381611807 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 381611807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 3.rv_dm_stress_all_with_rand_reset.107069466948516973825147447749245754575024332309592742203977734829531661187135
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1294350677 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 237953026 [0xe2ee002]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 1294350677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rv_dm_stress_all_with_rand_reset.33988275991317143550209509417414329811271986260083959794328001228054598402525
    Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 822997915 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1484021250 [0x58745e02]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 822997915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all has 1 failures.
  - 7.rv_dm_stress_all.31320986762024453490816730565349302582565239267138890231291900295353810654443
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 879130932 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 879130932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 22.rv_dm_stress_all_with_rand_reset.67254455820988921551241123317751067146772430098778295091036182892721920644173
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  13775354 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  13775354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test rv_dm_tap_fsm_rand_reset has 2 failures.

8.rv_dm_tap_fsm_rand_reset.67838933210834822143235164837671655151856659405924050224156102292692522969619
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 5600938021 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5600938021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.rv_dm_tap_fsm_rand_reset.113470711644414852300165524615472602627430006237085918839386590184482573223377
Line 391, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 21151258917 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 21151258917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 8.rv_dm_stress_all_with_rand_reset.12752800136468520613135978907369049556472800858344800992049292425672104404948
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  69912044 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
  UVM_INFO @  69912044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.rv_dm_stress_all_with_rand_reset.89874680557303354765015351687316900847729613898740149025672614901629567126154
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   7653991 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
  UVM_INFO @   7653991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 14.rv_dm_stress_all_with_rand_reset.23825924945475233093509310160782103630227306150626054761108368802344616935315
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  87468795 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (27 [0x1b] vs 700820507 [0x29c5ac1b])
  UVM_INFO @  87468795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 29.rv_dm_stress_all.1105978886159625951208267654845296308568250981926702312931166113006165934919
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2770753004 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (1 [0x1] vs 2958143569 [0xb051b051])
  UVM_INFO @ 2770753004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:41) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.73654875300392849373009510078360151638508948106402878771974760492141894608082
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 210184671 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 210184671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:74) [scoreboard] Check failed item.dout == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 3.rv_dm_stress_all.12414195810911864972982436740485655105654394887077758216971763000360175117533
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 8001386982 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (755914244098 [0xb000000002] vs 0 [0x0])
  UVM_INFO @ 8001386982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.31998201477744938798771527050951388032230477769797207359806411195702238860797
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 785143620 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
  UVM_INFO @ 785143620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:42) [rv_dm_halt_resume_whereto_vseq] Check failed * == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 15.rv_dm_stress_all_with_rand_reset.93073636858431780700008270584204353604360330948748581671089086392116001860763
    Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 946207950 ps: (rv_dm_halt_resume_whereto_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 946207950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_halted_vseq.sv:27) [rv_dm_mem_tl_access_halted_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 16.rv_dm_stress_all_with_rand_reset.111030214234994611491111549609136991999771698468790551686665025393587903304724
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 134615993 ps: (rv_dm_mem_tl_access_halted_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 134615993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 20.rv_dm_stress_all.91346616983307452080915374627673021796461136962378289612263920831781177331354
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @  22320033 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  22320033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 21.rv_dm_stress_all_with_rand_reset.111826713274919326327936063316573942560776881564920630785613502894772056291518
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2362126584 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x15c93100)
  UVM_INFO @ 2362126584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 24.rv_dm_stress_all.14408638888577227556011104326433471478364351151557794138480440120138021829694
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 344132781 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 344132781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to read csr/field jtag_dmi_ral.abstractdata_* has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 26.rv_dm_stress_all_with_rand_reset.78409864535582813938855879120440992780836574321091704259453741223132063421650
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6157841024 ps: (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to read csr/field jtag_dmi_ral.abstractdata_0
  UVM_INFO @ 6157841024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 41.rv_dm_stress_all.70299977878507093605300939303794470330140111772715733875703968318329022735197
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1243071128 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1243071128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```