RV_DM Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.910s 330.468us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.070s 185.803us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.900s 172.264us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 5.550s 2.986ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0.920s 73.065us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 4.250s 3.023ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 4.520s 2.367ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.082m 41.897ms 5 5 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 47.930s 18.119ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 13.800s 3.963ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 4.030s 3.779ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.450s 473.917us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.530s 455.067us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.950s 85.841us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.730s 377.382us 1 2 50.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.760s 130.315us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.710s 27.078us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 1.890s 653.853us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.760s 110.137us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.910s 76.361us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.450s 473.917us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.830s 52.310us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.500s 143.870us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.530s 224.516us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.155m 7.367ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.101m 4.401ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 8.330s 8.661ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.101m 4.401ms 5 5 100.00
rv_dm_csr_rw 2.530s 224.516us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.730s 40.120us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.740s 218.996us 5 5 100.00
V1 TOTAL 158 161 98.14
V2 idcode rv_dm_smoke 1.910s 330.468us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.130s 385.312us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.755m 50.000ms 0 2 0.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.020s 126.183us 2 2 100.00
V2 sba rv_dm_sba_tl_access 8.970s 3.250ms 1 20 5.00
rv_dm_delayed_resp_sba_tl_access 6.000s 3.304ms 2 20 10.00
V2 bad_sba rv_dm_bad_sba_tl_access 5.040s 2.519ms 1 20 5.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 42.770s 50.000ms 1 20 5.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.000s 442.694us 1 2 50.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 1.780s 1.089ms 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 0.900s 262.314us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 7.230s 1.902ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 56.430s 16.230ms 17 40 42.50
V2 stress_all rv_dm_stress_all 14.800s 4.278ms 8 50 16.00
V2 alert_test rv_dm_alert_test 0.850s 18.008us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.280s 405.661us 19 20 95.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.280s 405.661us 19 20 95.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.101m 4.401ms 5 5 100.00
rv_dm_csr_hw_reset 2.500s 143.870us 5 5 100.00
rv_dm_csr_rw 2.530s 224.516us 20 20 100.00
rv_dm_same_csr_outstanding 8.090s 1.026ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.101m 4.401ms 5 5 100.00
rv_dm_csr_hw_reset 2.500s 143.870us 5 5 100.00
rv_dm_csr_rw 2.530s 224.516us 20 20 100.00
rv_dm_same_csr_outstanding 8.090s 1.026ms 20 20 100.00
V2 TOTAL 132 276 47.83
V2S tl_intg_err rv_dm_sec_cm 1.400s 286.363us 5 5 100.00
rv_dm_tl_intg_err 20.240s 3.987ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 17.800s 827.280us 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 315 512 61.52

Testplan Progress

Items Total Written Passing Progress
V1 28 28 26 92.86
V2 18 16 7 38.89
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
79.42 93.91 81.32 87.69 74.36 82.67 98.42 37.60

Failure Buckets

Past Results