RV_DM Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.210s	2.124ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.950s	1.687ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.890s	904.134us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	2.109m	50.644ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	4.050s	1.220ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	12.400s	4.671ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	39.610s	14.608ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.365m	51.783ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	8.666m	200.963ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.250s	867.504us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	9.410s	3.073ms	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	4.810s	2.557ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	3.500s	2.909ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	9.630s	3.644ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.980s	911.461us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.790s	83.579us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	7.040s	2.442ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.290s	1.506ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.990s	193.017us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.250s	662.551us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	4.810s	2.557ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.930s	68.446us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.810s	503.388us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.690s	233.084us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.103m	5.134ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.299m	15.629ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	11.320s	5.034ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.299m	15.629ms	5	5	100.00
		rv_dm_csr_rw	2.690s	233.084us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.170s	165.430us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.820s	82.781us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	3.210s	2.124ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	12.500s	4.660ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.960s	587.714us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	5.210s	1.982ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	33.040s	12.692ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	13.740s	4.609ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	46.430s	17.926ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.006m	68.807ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.930s	448.338us	2	2	100.00
V2	sba_debug_disabled	sba_debug_disabled			0	0	--
V2	ndmreset_req	rv_dm_ndmreset_req	3.340s	921.242us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.800s	437.509us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	16.840s	8.828ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	12.179m	300.000ms	0	10	0.00
V2	stress_all	rv_dm_stress_all	2.120h	10.000s	20	50	40.00
V2	alert_test	rv_dm_alert_test	1.090s	179.777us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.250s	514.903us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.250s	514.903us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.299m	15.629ms	5	5	100.00
		rv_dm_csr_hw_reset	2.810s	503.388us	5	5	100.00
		rv_dm_csr_rw	2.690s	233.084us	20	20	100.00
		rv_dm_same_csr_outstanding	8.360s	2.204ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.299m	15.629ms	5	5	100.00
		rv_dm_csr_hw_reset	2.810s	503.388us	5	5	100.00
		rv_dm_csr_rw	2.690s	233.084us	20	20	100.00
		rv_dm_same_csr_outstanding	8.360s	2.204ms	20	20	100.00
V2		TOTAL			205	246	83.33
V2S	tl_intg_err	rv_dm_sec_cm	4.690s	2.610ms	5	5	100.00
		rv_dm_tl_intg_err	28.520s	5.624ms	20	20	100.00
V2S	sec_cm_bus_integrity	sec_cm_bus_integrity			0	0	--
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sec_cm_lc_hw_debug_en_intersig_mubi			0	0	--
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	31.400s	1.996ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			406	457	88.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	16	13	72.22
V2S	10	2	2	20.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
78.00	94.81	78.48	88.43	62.82	84.33	98.42	38.72

Failure Buckets

Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test rv_dm_stress_all has 19 failures.
  - 0.rv_dm_stress_all.5192455537520544484621949060343678179109809428390925710976946501891423364944
    Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
```
  Job ID: smart:5a499fb9-b23a-4ea9-8dae-c9c0f5f92418
```
  - 4.rv_dm_stress_all.85611552478268659461366582475184415883218125662458528406857609674627194495889
    Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
```
  Job ID: smart:8f067719-9332-4269-a21d-c92d06edeedb
```
  - ... and 17 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 11 failures:
- Test rv_dm_stress_all has 10 failures.
  - 7.rv_dm_stress_all.53533042230936257319970908029799284769818801791016851609587762194256059399074
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.rv_dm_stress_all.96075556116432269292098580972991956541304979363138122911623874977670576820422
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 8.rv_dm_tap_fsm_rand_reset.43503441186958541743629091825242789077534622275032747144120850458306772311710
    Line 281, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 10 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.46706594651056099092599292524203251446898829429435841261700571211325310404714
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_FATAL @ 8827731631 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 8827731631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_tap_fsm_rand_reset has 9 failures.
  - 0.rv_dm_tap_fsm_rand_reset.53382749508105685986616383659001337115256992354674724445867010793271622019875
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 4430426544 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 4430426544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_tap_fsm_rand_reset.47674359341245341693316715950277209832726183660370202941570173323377807464980
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 3363545635 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 3363545635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:25) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 2.rv_dm_stress_all_with_rand_reset.4693442103911172810241979380732323272994982615707477573322828974721510468408
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1930360483 ps: (rv_dm_halt_resume_whereto_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1930360483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.40545886344677599930454366117048073643439190024517542673891562177625811479711
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 455574473 ps: (rv_dm_halt_resume_whereto_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 455574473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

7.rv_dm_stress_all_with_rand_reset.71670124336079057477187127459630069400208676106722584268998947410442944147600
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 678100749 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2667092507 [0x9ef89a1b] vs 296131099 [0x11a69a1b])
  UVM_INFO @ 678100749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.rv_dm_stress_all_with_rand_reset.20193548161796133606331342454864614923351537920696062662229376185508934682069
Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1995824093 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (950973654 [0x38aeb4d6] vs 950951126 [0x38ae5cd6])
  UVM_INFO @ 1995824093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.87298435330721038310604316140420683807034324358612583060149007250483886385442
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 627889990 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (33653 [0x8375] vs 0 [0x0])
  UVM_INFO @ 627889990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.58355728636226764629091632987421483009588470645150366194681887586588293953621
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1739770693 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 815783170 [0x309fdd02]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 1739770693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:38) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.72057300184150056969881264996995941063547185051678835291558842257287075815847
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1072371845 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1072371845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:40) [rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.89517446307374198661216802304231581319167157526769805465892069398358713327374
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 445548674 ps: (rv_dm_ndmreset_req_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 445548674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.3352123305712550083977408329832211849287831692283387905200570092224350186284
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 394758025 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (18 [0x12] vs 29558 [0x7376])
  UVM_INFO @ 394758025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:51) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.109941424951104575495250505793194637609511472151242596696861798322243284908588
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 117480752 ps: (rv_dm_ndmreset_req_vseq.sv:51) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
  UVM_INFO @ 117480752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:42) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 27.rv_dm_stress_all.45654664865111040677229235056986757168886720626721250946061078775906272300222
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 38324131738 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 38324131738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```