RV_DM Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.210s 2.124ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.950s 1.687ms 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.890s 904.134us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 2.109m 50.644ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 4.050s 1.220ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 12.400s 4.671ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 39.610s 14.608ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.365m 51.783ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 8.666m 200.963ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.250s 867.504us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 9.410s 3.073ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 4.810s 2.557ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 3.500s 2.909ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 9.630s 3.644ms 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.980s 911.461us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.790s 83.579us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 7.040s 2.442ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.290s 1.506ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.990s 193.017us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.250s 662.551us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 4.810s 2.557ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.930s 68.446us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.810s 503.388us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.690s 233.084us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.103m 5.134ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.299m 15.629ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 11.320s 5.034ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.299m 15.629ms 5 5 100.00
rv_dm_csr_rw 2.690s 233.084us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.170s 165.430us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.820s 82.781us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 3.210s 2.124ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 12.500s 4.660ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.960s 587.714us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 5.210s 1.982ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 33.040s 12.692ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 13.740s 4.609ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 46.430s 17.926ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 3.006m 68.807ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.930s 448.338us 2 2 100.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 3.340s 921.242us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.800s 437.509us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 16.840s 8.828ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 12.179m 300.000ms 0 10 0.00
V2 stress_all rv_dm_stress_all 2.120h 10.000s 20 50 40.00
V2 alert_test rv_dm_alert_test 1.090s 179.777us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.250s 514.903us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.250s 514.903us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.299m 15.629ms 5 5 100.00
rv_dm_csr_hw_reset 2.810s 503.388us 5 5 100.00
rv_dm_csr_rw 2.690s 233.084us 20 20 100.00
rv_dm_same_csr_outstanding 8.360s 2.204ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.299m 15.629ms 5 5 100.00
rv_dm_csr_hw_reset 2.810s 503.388us 5 5 100.00
rv_dm_csr_rw 2.690s 233.084us 20 20 100.00
rv_dm_same_csr_outstanding 8.360s 2.204ms 20 20 100.00
V2 TOTAL 205 246 83.33
V2S tl_intg_err rv_dm_sec_cm 4.690s 2.610ms 5 5 100.00
rv_dm_tl_intg_err 28.520s 5.624ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 31.400s 1.996ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 406 457 88.84

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 16 13 72.22
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
78.00 94.81 78.48 88.43 62.82 84.33 98.42 38.72

Failure Buckets

Past Results