RV_DM Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 4.870s 2.717ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.770s 369.202us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.780s 1.201ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 19.610s 7.316ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 4.690s 1.375ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 12.530s 4.420ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 18.580s 7.693ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.972m 76.525ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.221m 148.883ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.410s 269.073us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.910s 272.862us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.070s 555.031us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.960s 790.178us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.450s 276.145us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.530s 538.592us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.820s 165.434us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.710s 332.704us 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.540s 538.829us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.220s 238.718us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.990s 793.332us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.070s 555.031us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.820s 53.973us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.700s 483.825us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.540s 371.472us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.207m 20.547ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.303m 8.054ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 10.050s 4.208ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.303m 8.054ms 5 5 100.00
rv_dm_csr_rw 2.540s 371.472us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.020s 129.923us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.860s 91.274us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 4.870s 2.717ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 7.180s 2.618ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.150s 403.617us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.240s 1.094ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 23.100s 16.626ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 14.140s 5.084ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 28.920s 9.801ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.166m 83.723ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.000s 131.978us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 11.090s 4.541ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.630s 566.667us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.200s 533.932us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 23.940s 9.771ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 13.150s 13.264ms 0 10 0.00
V2 stress_all rv_dm_stress_all 49.830s 18.172ms 45 50 90.00
V2 alert_test rv_dm_alert_test 1.070s 130.128us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.670s 566.209us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.670s 566.209us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.303m 8.054ms 5 5 100.00
rv_dm_csr_hw_reset 2.700s 483.825us 5 5 100.00
rv_dm_csr_rw 2.540s 371.472us 20 20 100.00
rv_dm_same_csr_outstanding 7.950s 2.293ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.303m 8.054ms 5 5 100.00
rv_dm_csr_hw_reset 2.700s 483.825us 5 5 100.00
rv_dm_csr_rw 2.540s 371.472us 20 20 100.00
rv_dm_same_csr_outstanding 7.950s 2.293ms 20 20 100.00
V2 TOTAL 232 248 93.55
V2S tl_intg_err rv_dm_sec_cm 6.630s 2.356ms 5 5 100.00
rv_dm_tl_intg_err 24.100s 7.619ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 24.100s 7.619ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 11.090s 4.541ms 2 2 100.00
rv_dm_debug_disabled 0.930s 151.887us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.239m 45.193ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 435 461 94.36

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 14 77.78
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
81.38 95.27 79.03 88.93 67.95 85.17 98.32 55.01

Failure Buckets

Past Results