RV_DM Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	4.870s	2.717ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.770s	369.202us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.780s	1.201ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	19.610s	7.316ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	4.690s	1.375ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	12.530s	4.420ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	18.580s	7.693ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.972m	76.525ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.221m	148.883ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.410s	269.073us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.910s	272.862us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.070s	555.031us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.960s	790.178us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.450s	276.145us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.530s	538.592us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.820s	165.434us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.710s	332.704us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.540s	538.829us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.220s	238.718us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.990s	793.332us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.070s	555.031us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.820s	53.973us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.700s	483.825us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.540s	371.472us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.207m	20.547ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.303m	8.054ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	10.050s	4.208ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.303m	8.054ms	5	5	100.00
		rv_dm_csr_rw	2.540s	371.472us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.020s	129.923us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.860s	91.274us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	4.870s	2.717ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	7.180s	2.618ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.150s	403.617us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.240s	1.094ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	23.100s	16.626ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	14.140s	5.084ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	28.920s	9.801ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.166m	83.723ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.000s	131.978us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	11.090s	4.541ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.630s	566.667us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.200s	533.932us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	23.940s	9.771ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	13.150s	13.264ms	0	10	0.00
V2	stress_all	rv_dm_stress_all	49.830s	18.172ms	45	50	90.00
V2	alert_test	rv_dm_alert_test	1.070s	130.128us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.670s	566.209us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.670s	566.209us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.303m	8.054ms	5	5	100.00
		rv_dm_csr_hw_reset	2.700s	483.825us	5	5	100.00
		rv_dm_csr_rw	2.540s	371.472us	20	20	100.00
		rv_dm_same_csr_outstanding	7.950s	2.293ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.303m	8.054ms	5	5	100.00
		rv_dm_csr_hw_reset	2.700s	483.825us	5	5	100.00
		rv_dm_csr_rw	2.540s	371.472us	20	20	100.00
		rv_dm_same_csr_outstanding	7.950s	2.293ms	20	20	100.00
V2		TOTAL			232	248	93.55
V2S	tl_intg_err	rv_dm_sec_cm	6.630s	2.356ms	5	5	100.00
		rv_dm_tl_intg_err	24.100s	7.619ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	24.100s	7.619ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	11.090s	4.541ms	2	2	100.00
		rv_dm_debug_disabled	0.930s	151.887us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.239m	45.193ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			435	461	94.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	14	77.78
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
81.38	95.27	79.03	88.93	67.95	85.17	98.32	55.01

Failure Buckets

UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 11 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.38809158710339945086772077069652632413913117105194286227104954821242819238184
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_FATAL @ 9771093416 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 9771093416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_tap_fsm_rand_reset has 10 failures.
  - 0.rv_dm_tap_fsm_rand_reset.36878575742715601080715354162139427299069740807936308566830542803547259126628
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 4025612800 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 4025612800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_tap_fsm_rand_reset.33479335736991717972253236883745224152260997783798875275962768085538153867773
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 6805444232 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 6805444232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:31) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 4 failures:

Test rv_dm_stress_all_with_rand_reset has 3 failures.

0.rv_dm_stress_all_with_rand_reset.101354058408364353384511455899099464784875476914705857566638030360183217284848
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1010277888 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 1010277888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rv_dm_stress_all_with_rand_reset.71058594578190067145632272798470701520650719995047364230647719672739290404431
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2738910449 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 2738910449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rv_dm_stress_all has 1 failures.

5.rv_dm_stress_all.71882668664288694205822069239846052281127246173389841777604506233908697656120
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1977471129 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 1977471129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (rv_dm_scoreboard.sv:325) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 4.rv_dm_stress_all_with_rand_reset.75095191380390990572028503205082431380382586040066170611284040700659665318889
    Line 273, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3322234675 ps: (rv_dm_scoreboard.sv:325) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
  UVM_INFO @ 3322234675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_dm_stress_all_with_rand_reset.100391691905882672949028849486428445856527310232256303024391614892933591368996
    Line 309, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 45192799922 ps: (rv_dm_scoreboard.sv:325) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
  UVM_INFO @ 45192799922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)' has 2 failures:

Test rv_dm_stress_all has 2 failures.

16.rv_dm_stress_all.48006513924669148188486740275270655236707971840678999632565465032951005019491
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 5383614689 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 5383614689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.rv_dm_stress_all.49430296814494107557573968080701001043436622937664361555437709987956486801166
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 521372129 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 521372129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:42) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all has 2 failures.

18.rv_dm_stress_all.28770126489355313939368458493173952542496605773048771318489777326979420511260
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 3455430150 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 3455430150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.rv_dm_stress_all.45169475896151856181034170120987902152988289576446803440580403490387888305635
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 8964435203 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 8964435203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.49574356331920973462581731399550309203546085106769356753827602679924886187561
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1864692881 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (31 [0x1f] vs 3806640159 [0xe2e4b81f])
  UVM_INFO @ 1864692881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:244) [rv_dm_halt_resume_whereto_vseq] Check failed (!dmcontrol_val.ndmreset) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.24139658378034645344839550293422036475046191104641118207442959966513430919892
    Line 271, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1768358760 ps: (rv_dm_base_vseq.sv:244) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed (!dmcontrol_val.ndmreset)
  UVM_INFO @ 1768358760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_halted_vseq.sv:30) [rv_dm_mem_tl_access_halted_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.43274796820877455637784427807288065937563707476973899781676614427620128532388
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1349785603 ps: (rv_dm_mem_tl_access_halted_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1349785603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:28) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.113104476605894878906314786235552218664688332527826994005984497885438830216821
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 746789493 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 746789493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (rv_dm_scoreboard.sv:325) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.55731000677130747290257674304613566811464486726236324496832918857438985604559
    Line 285, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 104272928314 ps: (rv_dm_scoreboard.sv:325) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 104272928314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```