RV_DM Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.890s	1.052ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.940s	878.716us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.910s	996.725us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	2.077m	49.325ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.830s	2.109ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	23.850s	9.942ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	18.580s	6.820ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.297m	57.489ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.087m	75.400ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	4.360s	1.322ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	3.110s	1.043ms	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.040s	538.378us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	11.620s	4.019ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.310s	651.215us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	4.120s	2.414ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.290s	369.672us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.680s	1.721ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	21.840s	7.898ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.900s	144.491us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.000s	195.484us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.040s	538.378us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.180s	156.726us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.350s	436.084us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.840s	503.866us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.252m	23.268ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.285m	10.626ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	7.600s	4.782ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.285m	10.626ms	5	5	100.00
		rv_dm_csr_rw	2.840s	503.866us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.990s	127.616us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.830s	124.959us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	1.890s	1.052ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	6.110s	2.312ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.920s	398.335us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	6.280s	2.119ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	42.500s	15.343ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	26.250s	9.139ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	17.670s	6.260ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	6.654m	300.000ms	19	20	95.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	3.750s	1.131ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	4.330s	1.520ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.070s	439.133us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.200s	242.566us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	9.310s	7.195ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	48.640s	14.347ms	0	10	0.00
V2	stress_all	rv_dm_stress_all	37.230s	13.302ms	43	50	86.00
V2	alert_test	rv_dm_alert_test	1.210s	205.181us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.560s	4.463ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.560s	4.463ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.285m	10.626ms	5	5	100.00
		rv_dm_csr_hw_reset	3.350s	436.084us	5	5	100.00
		rv_dm_csr_rw	2.840s	503.866us	20	20	100.00
		rv_dm_same_csr_outstanding	9.560s	6.539ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.285m	10.626ms	5	5	100.00
		rv_dm_csr_hw_reset	3.350s	436.084us	5	5	100.00
		rv_dm_csr_rw	2.840s	503.866us	20	20	100.00
		rv_dm_same_csr_outstanding	9.560s	6.539ms	20	20	100.00
V2		TOTAL			229	248	92.34
V2S	tl_intg_err	rv_dm_sec_cm	6.380s	2.031ms	5	5	100.00
		rv_dm_tl_intg_err	32.620s	6.326ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	32.620s	6.326ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	4.330s	1.520ms	2	2	100.00
		rv_dm_debug_disabled	0.830s	96.195us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	22.060s	2.476ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			432	461	93.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	13	72.22
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
81.22	95.27	79.17	88.93	66.67	85.17	98.32	55.01

Failure Buckets

UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 11 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.244823627525771380925375549723669819233403200048107679848311712047428452965
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_FATAL @ 7194957605 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 7194957605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_tap_fsm_rand_reset has 10 failures.
  - 0.rv_dm_tap_fsm_rand_reset.80172481130804058897877952760976827006422355547261675094757683349823706937591
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 5437661812 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 5437661812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_tap_fsm_rand_reset.71235124743230772357127591526709496143218445349239916536006908904074494770065
    Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 9309259919 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 9309259919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)' has 4 failures:

Test rv_dm_stress_all has 4 failures.

12.rv_dm_stress_all.107041869134330614743645453224688854769235313122382138965843749802478222146366
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 5153039116 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 5153039116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.rv_dm_stress_all.64886682779330174842094046498636622996257353120433832152895148636298964680391
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 6621559578 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 6621559578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 3 failures:

Test rv_dm_stress_all_with_rand_reset has 3 failures.

0.rv_dm_stress_all_with_rand_reset.113998958261754377456110556182953586835054652968401862089004145166192220708705
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1671246339 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 3895779658 [0xe834e14a])
  UVM_INFO @ 1671246339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rv_dm_stress_all_with_rand_reset.36298540431500731527598432066985914205250149983729070979911371200361911911846
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 718558762 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3053205433 [0xb5fc37b9] vs 3042523043 [0xb55937a3])
  UVM_INFO @ 718558762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:31) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 3 failures:

Test rv_dm_stress_all has 2 failures.

5.rv_dm_stress_all.94949956479229689959728990908887767170779904244636159773024250472415368022143
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2425974613 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 2425974613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.rv_dm_stress_all.36224213208657681674352664393962608289511972229022341419316419417301430419310
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1201173906 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 1201173906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all_with_rand_reset has 1 failures.

6.rv_dm_stress_all_with_rand_reset.9659179194998406887821082072307591619930617648078405257003266628784836924230
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1289348805 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1289348805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:42) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 5.rv_dm_stress_all_with_rand_reset.4787186384542005630464023927949419362812157279341557141273162914560419065293
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3630478646 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 3630478646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_dm_stress_all_with_rand_reset.99348615637517591361064766802827425862846482806555860295535699764647550365777
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 140890414 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 1 [0x1])
  UVM_INFO @ 140890414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 19.rv_dm_stress_all.72032466235567379551213910239235406445793619704670822522708292816375709494752
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 836129906 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 836129906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:38) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 2.rv_dm_stress_all_with_rand_reset.108903366352785523367218422269684808529056289687096384197488289287962160338471
    Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1965701222 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1965701222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rv_dm_stress_all_with_rand_reset.6945601531864763302960943402859047289006357817533319802627054633487501819541
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3928571812 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3928571812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (rv_dm_scoreboard.sv:325) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.32765987653406794556705621511167310248381435201607290422817647008281088914616
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1251082157 ps: (rv_dm_scoreboard.sv:325) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 1251082157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 9.rv_dm_stress_all_with_rand_reset.91681571891170903224984932179243902884887440049099626223177089310623807942597
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2476076701 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (4 [0x4] vs 2399141892 [0x8f000004])
  UVM_INFO @ 2476076701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rv_dm_autoincr_sba_tl_access has 1 failures.
  - 11.rv_dm_autoincr_sba_tl_access.69389439764124812131646837977157645368732319206757315226288807299480791295067
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```