RV_DM Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.890s 1.052ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.940s 878.716us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.910s 996.725us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 2.077m 49.325ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.830s 2.109ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 23.850s 9.942ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 18.580s 6.820ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.297m 57.489ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.087m 75.400ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 4.360s 1.322ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 3.110s 1.043ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.040s 538.378us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 11.620s 4.019ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.310s 651.215us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 4.120s 2.414ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.290s 369.672us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.680s 1.721ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 21.840s 7.898ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.900s 144.491us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.000s 195.484us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.040s 538.378us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 1.180s 156.726us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.350s 436.084us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.840s 503.866us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.252m 23.268ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.285m 10.626ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 7.600s 4.782ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.285m 10.626ms 5 5 100.00
rv_dm_csr_rw 2.840s 503.866us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.990s 127.616us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.830s 124.959us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 1.890s 1.052ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 6.110s 2.312ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.920s 398.335us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 6.280s 2.119ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 42.500s 15.343ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 26.250s 9.139ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 17.670s 6.260ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 6.654m 300.000ms 19 20 95.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 3.750s 1.131ms 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 4.330s 1.520ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.070s 439.133us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.200s 242.566us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 9.310s 7.195ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 48.640s 14.347ms 0 10 0.00
V2 stress_all rv_dm_stress_all 37.230s 13.302ms 43 50 86.00
V2 alert_test rv_dm_alert_test 1.210s 205.181us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.560s 4.463ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.560s 4.463ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.285m 10.626ms 5 5 100.00
rv_dm_csr_hw_reset 3.350s 436.084us 5 5 100.00
rv_dm_csr_rw 2.840s 503.866us 20 20 100.00
rv_dm_same_csr_outstanding 9.560s 6.539ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.285m 10.626ms 5 5 100.00
rv_dm_csr_hw_reset 3.350s 436.084us 5 5 100.00
rv_dm_csr_rw 2.840s 503.866us 20 20 100.00
rv_dm_same_csr_outstanding 9.560s 6.539ms 20 20 100.00
V2 TOTAL 229 248 92.34
V2S tl_intg_err rv_dm_sec_cm 6.380s 2.031ms 5 5 100.00
rv_dm_tl_intg_err 32.620s 6.326ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 32.620s 6.326ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 4.330s 1.520ms 2 2 100.00
rv_dm_debug_disabled 0.830s 96.195us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 22.060s 2.476ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 432 461 93.71

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 13 72.22
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
81.22 95.27 79.17 88.93 66.67 85.17 98.32 55.01

Failure Buckets

Past Results