RV_DM Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	7.550s	2.832ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.020s	1.247ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.460s	647.255us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	31.700s	22.420ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.040s	1.904ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	8.700s	2.705ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	24.150s	9.172ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.381m	114.197ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.998m	56.133ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.330s	733.461us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.360s	239.166us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.910s	1.436ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	3.240s	1.626ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	3.300s	1.679ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.460s	331.822us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.070s	139.001us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.850s	362.119us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	3.510s	2.888ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.950s	510.835us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.110s	211.864us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.910s	1.436ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.880s	51.553us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.290s	302.887us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.640s	369.668us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.217m	23.586ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.251m	13.299ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	10.730s	4.188ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.251m	13.299ms	5	5	100.00
		rv_dm_csr_rw	2.640s	369.668us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.730s	63.220us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.790s	66.940us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	7.550s	2.832ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	5.750s	3.122ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.180s	390.595us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	6.160s	2.132ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	24.700s	9.079ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	21.870s	7.135ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	23.560s	15.997ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.470m	78.477ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.210s	684.464us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	2.370s	696.084us	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.170s	197.117us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.760s	803.333us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	1.530s	1.926ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	1.496m	35.382ms	7	10	70.00
V2	stress_all	rv_dm_stress_all	32.100s	12.489ms	43	50	86.00
V2	alert_test	rv_dm_alert_test	0.980s	138.228us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.710s	5.247ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.710s	5.247ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.251m	13.299ms	5	5	100.00
		rv_dm_csr_hw_reset	2.290s	302.887us	5	5	100.00
		rv_dm_csr_rw	2.640s	369.668us	20	20	100.00
		rv_dm_same_csr_outstanding	8.160s	780.510us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.251m	13.299ms	5	5	100.00
		rv_dm_csr_hw_reset	2.290s	302.887us	5	5	100.00
		rv_dm_csr_rw	2.640s	369.668us	20	20	100.00
		rv_dm_same_csr_outstanding	8.160s	780.510us	20	20	100.00
V2		TOTAL			237	248	95.56
V2S	tl_intg_err	rv_dm_sec_cm	7.370s	2.444ms	5	5	100.00
		rv_dm_tl_intg_err	26.620s	6.218ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	26.620s	6.218ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	2.370s	696.084us	2	2	100.00
		rv_dm_debug_disabled	0.940s	74.016us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	3.627m	69.055ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			440	461	95.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	14	77.78
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.84	95.27	79.59	89.42	74.36	85.50	98.42	57.31

Failure Buckets

Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)' has 5 failures:

Test rv_dm_stress_all has 5 failures.

13.rv_dm_stress_all.77592757988898329269149017492301908287461642134261826102896093884254766100616
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 1043447950 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1043447950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.rv_dm_stress_all.16791111216946040036209315386212361603358360548948722260603889607349092858237
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 3110928858 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 3110928858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 4 failures:
- Test rv_dm_stress_all_with_rand_reset has 4 failures.
  - 2.rv_dm_stress_all_with_rand_reset.67344257274133606624782501806039793675651206085206094877363389416242277950229
    Line 358, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 69055430085 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 69055430085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_dm_stress_all_with_rand_reset.81542076428107395765763593303283231918228492725062204916837668563311115593586
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6275435036 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 6275435036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:31) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 4 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

4.rv_dm_stress_all_with_rand_reset.95450110341042020032322644137222791124526583449597396203452495155713376039551
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3434716760 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 3434716760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rv_dm_stress_all_with_rand_reset.63344109679162248879250664258429806922770470831883992600064790407100236221579
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1071477672 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 1071477672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all has 2 failures.

15.rv_dm_stress_all.66980969496555285025251793472042571476313176116030518509819530976586961442163
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 5882180009 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 5882180009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.rv_dm_stress_all.109948682270329339569123396049658745040008888410255198054953097079026591421276
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 10831881252 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 10831881252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 3 failures:

Test rv_dm_tap_fsm_rand_reset has 3 failures.

1.rv_dm_tap_fsm_rand_reset.107732129234381645876272916971568662071367971801812797940903936609100809891110
Line 287, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 8882421727 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 8882421727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rv_dm_tap_fsm_rand_reset.96517793075776355928107472233296025967823070302539696380202362077242955526612
Line 360, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 35381863352 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 35381863352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:42) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 0.rv_dm_stress_all_with_rand_reset.106095449303647923909713752236787675409908104868727431682927183949498284297716
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 251256713 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 251256713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rv_dm_stress_all_with_rand_reset.6758618928599662801880506081430801114064243907438799626844502643494823599963
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5210142682 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 5210142682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

1.rv_dm_stress_all_with_rand_reset.1294789442954248419847071748056569366328014691430308422572099635235512442720
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2780025989 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (746579846 [0x2c7fe786] vs 746579884 [0x2c7fe7ac])
  UVM_INFO @ 2780025989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.rv_dm_stress_all_with_rand_reset.40683579632445584201756061764778663165013207506205630488970227432566055579615
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 706079673 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3356758608 [0xc8141250])
  UVM_INFO @ 706079673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.57162657826488113794816127030633420042780658116315944166419713662530709826908
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_ERROR @ 1925965306 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (0 [0x0] vs 3243850512 [0xc1593b10])
  UVM_INFO @ 1925965306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```