RV_DM Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	5.120s	1.321ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	7.700s	1.405ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.680s	561.917us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	58.490s	17.727ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	15.130s	2.542ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	34.160s	9.540ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	21.640s	6.866ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.773m	34.369ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.245m	43.118ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	3.840s	1.101ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.900s	171.572us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.630s	372.186us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.850s	775.904us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.620s	193.834us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.850s	414.997us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.940s	317.362us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	3.060s	516.381us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	3.840s	1.101ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.280s	97.975us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.900s	228.749us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.630s	372.186us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.310s	85.322us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.830s	555.079us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	4.850s	1.745ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.348m	36.410ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.475m	21.616ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.400s	199.639us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.475m	21.616ms	5	5	100.00
		rv_dm_csr_rw	4.850s	1.745ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.140s	35.111us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.180s	32.111us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	5.120s	1.321ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.280s	445.894us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.390s	238.815us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.690s	241.137us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	4.680s	1.105ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	26.610s	11.318ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	38.710s	11.345ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	34.490s	14.891ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.813m	60.807ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	5.280s	725.924us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	16.550s	4.977ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.660s	639.499us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.420s	65.818us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	29.400s	6.743ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.631m	3.928ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.060s	269.142us	1	1	100.00
V2	stress_all	rv_dm_stress_all	25.980s	5.747ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.730s	145.274us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	8.290s	147.583us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	8.290s	147.583us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.475m	21.616ms	5	5	100.00
		rv_dm_csr_hw_reset	3.830s	555.079us	5	5	100.00
		rv_dm_csr_rw	4.850s	1.745ms	20	20	100.00
		rv_dm_same_csr_outstanding	12.600s	10.271ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.475m	21.616ms	5	5	100.00
		rv_dm_csr_hw_reset	3.830s	555.079us	5	5	100.00
		rv_dm_csr_rw	4.850s	1.745ms	20	20	100.00
		rv_dm_same_csr_outstanding	12.600s	10.271ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	5.710s	2.707ms	5	5	100.00
		rv_dm_tl_intg_err	39.160s	6.493ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	39.160s	6.493ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	16.550s	4.977ms	2	2	100.00
		rv_dm_debug_disabled	1.780s	125.133us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	16.550s	4.977ms	2	2	100.00
		rv_dm_debug_disabled	1.780s	125.133us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	5.120s	1.321ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	3.690s	478.030us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.270s	320.129us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.270s	320.129us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	3.690s	478.030us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.659m	3.932ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.860s	42.765us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.49	96.34	89.82	92.10	94.67	90.27	98.74	57.49

Past Results

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