RV_DM Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.980s	1.269ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.770s	572.215us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.510s	369.793us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	53.900s	18.227ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	4.080s	2.414ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	35.470s	13.707ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	53.080s	11.926ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	4.881m	100.023ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.718m	114.637ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	4.860s	1.160ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	5.070s	664.794us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.560s	382.063us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.970s	680.046us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.220s	471.808us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.660s	213.378us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.420s	48.836us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.960s	865.532us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	4.860s	1.160ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.570s	191.434us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	3.110s	1.035ms	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.560s	382.063us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.420s	93.298us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.810s	151.192us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.430s	247.586us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.175m	6.745ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.259m	8.592ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.010s	236.145us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.259m	8.592ms	5	5	100.00
		rv_dm_csr_rw	3.430s	247.586us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.140s	138.185us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.390s	96.656us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	3.980s	1.269ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	3.190s	429.897us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	5.310s	653.963us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.130s	236.072us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.920s	325.592us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	26.660s	10.534ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	26.530s	6.451ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	1.003m	14.814ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	4.703m	69.921ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.240s	212.540us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	5.440s	3.134ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.810s	824.219us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.910s	165.786us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	24.450s	10.195ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.933m	45.027ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.310s	126.078us	1	1	100.00
V2	stress_all	rv_dm_stress_all	19.720s	5.898ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.680s	106.743us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.750s	223.695us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.750s	223.695us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.259m	8.592ms	5	5	100.00
		rv_dm_csr_hw_reset	2.810s	151.192us	5	5	100.00
		rv_dm_csr_rw	3.430s	247.586us	20	20	100.00
		rv_dm_same_csr_outstanding	9.400s	520.062us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.259m	8.592ms	5	5	100.00
		rv_dm_csr_hw_reset	2.810s	151.192us	5	5	100.00
		rv_dm_csr_rw	3.430s	247.586us	20	20	100.00
		rv_dm_same_csr_outstanding	9.400s	520.062us	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	4.390s	983.157us	5	5	100.00
		rv_dm_tl_intg_err	26.530s	7.434ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	26.530s	7.434ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	5.440s	3.134ms	2	2	100.00
		rv_dm_debug_disabled	1.490s	76.819us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	5.440s	3.134ms	2	2	100.00
		rv_dm_debug_disabled	1.490s	76.819us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.980s	1.269ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	3.740s	657.414us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.790s	253.904us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.790s	253.904us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	3.740s	657.414us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	57.100s	21.550ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.950s	117.508us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.33	96.34	89.82	92.10	93.33	90.27	98.74	57.72

Past Results

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