RV_DM Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.140s	678.257us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.900s	367.494us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.640s	776.033us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	51.140s	17.277ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	10.040s	1.442ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	22.400s	3.504ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	27.890s	5.878ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	4.511m	83.025ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.907m	73.363ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.540s	221.025us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.540s	175.385us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.980s	324.603us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	3.300s	848.182us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.520s	451.713us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.830s	654.632us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.260s	320.933us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	4.290s	719.855us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.540s	221.025us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.660s	165.320us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.480s	268.731us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.980s	324.603us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.650s	94.878us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	6.210s	527.462us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.730s	127.805us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.423m	29.174ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.700m	7.934ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.000s	156.662us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.700m	7.934ms	5	5	100.00
		rv_dm_csr_rw	3.730s	127.805us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.290s	148.828us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.550s	95.316us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	3.140s	678.257us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.670s	311.273us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.240s	151.595us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.200s	569.212us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.970s	576.268us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	36.360s	9.490ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	18.920s	5.652ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	50.750s	15.834ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.203m	39.861ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.340s	384.203us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	9.590s	3.185ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.970s	467.219us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.420s	247.394us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	33.590s	11.493ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.956m	10.855ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.120s	96.074us	1	1	100.00
V2	stress_all	rv_dm_stress_all	27.370s	8.027ms	49	50	98.00
V2	alert_test	rv_dm_alert_test	1.450s	88.844us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	8.840s	3.360ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	8.840s	3.360ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.700m	7.934ms	5	5	100.00
		rv_dm_csr_hw_reset	6.210s	527.462us	5	5	100.00
		rv_dm_csr_rw	3.730s	127.805us	20	20	100.00
		rv_dm_same_csr_outstanding	12.420s	713.963us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.700m	7.934ms	5	5	100.00
		rv_dm_csr_hw_reset	6.210s	527.462us	5	5	100.00
		rv_dm_csr_rw	3.730s	127.805us	20	20	100.00
		rv_dm_same_csr_outstanding	12.420s	713.963us	20	20	100.00
V2		TOTAL			250	251	99.60
V2S	tl_intg_err	rv_dm_sec_cm	4.880s	1.484ms	5	5	100.00
		rv_dm_tl_intg_err	34.550s	3.524ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	34.550s	3.524ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	9.590s	3.185ms	2	2	100.00
		rv_dm_debug_disabled	1.500s	118.058us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	9.590s	3.185ms	2	2	100.00
		rv_dm_debug_disabled	1.500s	118.058us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.140s	678.257us	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	3.460s	727.761us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.620s	282.710us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.620s	282.710us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	3.460s	727.761us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.280m	5.375ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	1.050s	18.294us	1	1	100.00
		TOTAL			482	483	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	18	94.74
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.11	96.64	90.24	92.10	93.33	90.44	98.22	62.76

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:268) [rv_dm_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
  • Test rv_dm_stress_all has 1 failures.

    • 0.rv_dm_stress_all.62974317406988931825110671456284761130994339005485315652979342319751388721820
      Line 76, in log /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log

        UVM_FATAL @ 10595887077 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Timeout waiting tl_access : addr=0xff9ac008
        UVM_INFO @ 10595887077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.10.10_10.17.56
• 2024.10.04_00.44.46
• 2024.09.25_11.03.48
• 2024.09.19_09.07.30
• 2024.09.12_10.19.07
• 2024.09.10_08.13.53