RV_DM Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.640s	1.388ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.520s	604.715us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	5.280s	843.223us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.052m	20.365ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	7.370s	2.127ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	36.330s	6.224ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	27.410s	5.199ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.533m	34.206ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	7.265m	138.077ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.660s	1.002ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	4.920s	712.482us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.180s	391.986us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.650s	493.000us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.520s	92.067us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	7.800s	1.654ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.240s	200.231us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	3.500s	574.834us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.660s	1.002ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.320s	467.280us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.670s	368.862us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.180s	391.986us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.270s	65.856us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.800s	364.069us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.710s	145.368us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.389m	8.733ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.643m	4.113ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.960s	434.954us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.643m	4.113ms	5	5	100.00
		rv_dm_csr_rw	3.710s	145.368us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.630s	107.298us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.360s	72.234us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	3.640s	1.388ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.690s	272.340us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.450s	347.205us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.960s	280.303us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.870s	355.430us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	47.920s	16.649ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	59.280s	13.967ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	46.310s	16.198ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	6.869m	127.488ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.140s	293.092us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	9.220s	5.251ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.790s	167.494us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	3.000s	365.673us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	9.860s	9.245ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.537m	5.831ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.300s	95.906us	1	1	100.00
V2	stress_all	rv_dm_stress_all	33.990s	9.714ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.780s	172.369us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	8.650s	329.251us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	8.650s	329.251us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.643m	4.113ms	5	5	100.00
		rv_dm_csr_hw_reset	3.800s	364.069us	5	5	100.00
		rv_dm_csr_rw	3.710s	145.368us	20	20	100.00
		rv_dm_same_csr_outstanding	11.440s	1.674ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.643m	4.113ms	5	5	100.00
		rv_dm_csr_hw_reset	3.800s	364.069us	5	5	100.00
		rv_dm_csr_rw	3.710s	145.368us	20	20	100.00
		rv_dm_same_csr_outstanding	11.440s	1.674ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	4.830s	645.120us	5	5	100.00
		rv_dm_tl_intg_err	37.860s	4.868ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	37.860s	4.868ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	9.220s	5.251ms	2	2	100.00
		rv_dm_debug_disabled	1.280s	67.931us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	9.220s	5.251ms	2	2	100.00
		rv_dm_debug_disabled	1.280s	67.931us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.640s	1.388ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	4.010s	675.830us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.520s	140.601us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.520s	140.601us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	4.010s	675.830us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.640m	25.223ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	1.000s	21.565us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.01	96.34	90.10	92.10	93.33	90.27	98.63	55.30

Past Results

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