RV_DM Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	29.190s	10.767ms	1	2	50.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	6.290s	848.148us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	5.410s	667.995us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.562m	14.816ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	8.970s	2.385ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	42.240s	10.801ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	32.290s	6.378ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.609m	26.207ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	6.605m	219.935ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.770s	1.384ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.590s	860.049us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.090s	859.343us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.740s	507.009us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.310s	497.148us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.080s	1.748ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.430s	129.556us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.250s	703.531us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.770s	1.384ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.660s	454.954us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.750s	954.224us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.090s	859.343us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.960s	57.265us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	4.580s	629.611us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	4.110s	1.313ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.212m	20.078ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.689m	13.525ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	6.310s	128.432us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.689m	13.525ms	5	5	100.00
		rv_dm_csr_rw	4.110s	1.313ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.440s	76.586us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.250s	46.728us	5	5	100.00
V1		TOTAL			179	180	99.44
V2	idcode	rv_dm_smoke	29.190s	10.767ms	1	2	50.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.830s	687.136us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.970s	314.170us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.980s	122.835us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.510s	609.961us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	21.810s	7.198ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	25.900s	7.479ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	31.070s	10.093ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	4.263m	70.158ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.040s	109.461us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	4.170s	1.089ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.440s	345.200us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.760s	350.813us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	18.630s	17.544ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	1.590m	8.892ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.940s	56.984us	1	1	100.00
V2	stress_all	rv_dm_stress_all	27.120s	9.713ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.700s	157.061us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.840s	998.526us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.840s	998.526us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.689m	13.525ms	5	5	100.00
		rv_dm_csr_hw_reset	4.580s	629.611us	5	5	100.00
		rv_dm_csr_rw	4.110s	1.313ms	20	20	100.00
		rv_dm_same_csr_outstanding	12.380s	2.222ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.689m	13.525ms	5	5	100.00
		rv_dm_csr_hw_reset	4.580s	629.611us	5	5	100.00
		rv_dm_csr_rw	4.110s	1.313ms	20	20	100.00
		rv_dm_same_csr_outstanding	12.380s	2.222ms	20	20	100.00
V2		TOTAL			250	251	99.60
V2S	tl_intg_err	rv_dm_sec_cm	2.810s	2.613ms	5	5	100.00
		rv_dm_tl_intg_err	29.940s	5.055ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	29.940s	5.055ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	4.170s	1.089ms	2	2	100.00
		rv_dm_debug_disabled	1.040s	47.409us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	4.170s	1.089ms	2	2	100.00
		rv_dm_debug_disabled	1.040s	47.409us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	29.190s	10.767ms	1	2	50.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.140s	407.184us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.760s	273.465us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.760s	273.465us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.140s	407.184us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.350m	7.081ms	9	10	90.00
V3		TOTAL			9	10	90.00
	Unmapped tests	rv_dm_scanmode	0.750s	22.557us	1	1	100.00
		TOTAL			480	483	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	26	96.30
V2	19	19	18	94.74
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.98	96.64	90.52	92.10	93.33	90.44	98.74	61.10

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:268) [rv_dm_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rv_dm_smoke has 1 failures.
  - 0.rv_dm_smoke.95035483946151768504786981728463179889371232920934133966378823794952304096480
    Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log
```
  UVM_FATAL @ 10767129587 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Timeout waiting tl_access : addr=0xb7ca5f0c
  UVM_INFO @ 10767129587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [seq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.3368263779001603461287886522738799957726644103852793707316093409460906536123
    Line 86, in log /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_FATAL @ 17544365207 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Timeout waiting tl_access : addr=0xd64ba8e3
  UVM_INFO @ 17544365207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:391) [rv_dm_jtag_dtm_idle_hint_vseq] Check failed expected_dmistat == get_field_val(jtag_dtm_ral.dtmcs.dmistat, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.47827622650148026555573400575584713872437981306053537302335121813098790426288
    Line 151, in log /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3353624485 ps: (rv_dm_base_vseq.sv:391) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_idle_hint_vseq] Check failed expected_dmistat == get_field_val(jtag_dtm_ral.dtmcs.dmistat, rdata) (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 3353624485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_DM Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `29d22a60a2`