RV_TIMER Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	45.173m	146.914ms	193	200	96.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.600s	18.116us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.650s	32.830us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.250s	91.057us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.760s	27.149us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.670s	35.405us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.650s	32.830us	20	20	100.00
		rv_timer_csr_aliasing	0.760s	27.149us	5	5	100.00
V1		TOTAL			248	255	97.25
V2	random_reset	rv_timer_random_reset	29.181m	56.741ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.036m	412.331ms	50	50	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	17.465m	4.279s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	17.465m	4.279s	50	50	100.00
V2	stress	rv_timer_stress_all	1.185h	780.356ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.620s	56.446us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.880s	610.559us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.880s	610.559us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.600s	18.116us	5	5	100.00
		rv_timer_csr_rw	0.650s	32.830us	20	20	100.00
		rv_timer_csr_aliasing	0.760s	27.149us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	129.925us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.600s	18.116us	5	5	100.00
		rv_timer_csr_rw	0.650s	32.830us	20	20	100.00
		rv_timer_csr_aliasing	0.760s	27.149us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	129.925us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	0.830s	55.832us	5	5	100.00
		rv_timer_tl_intg_err	1.400s	243.187us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.400s	243.187us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	26.212m	136.032ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			612	620	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.59	99.38	98.73	100.00	--	100.00	100.00	99.43

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 8 failures:

Test rv_timer_random has 7 failures.

37.rv_timer_random.1024436296
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.rv_timer_random.247941101
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test rv_timer_stress_all has 1 failures.

42.rv_timer_stress_all.3976278785
Line 245, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---