748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 43.860m | 300.119ms | 171 | 200 | 85.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.700s | 67.350us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.670s | 34.589us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.270s | 291.256us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.790s | 21.285us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.560s | 440.381us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.670s | 34.589us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.790s | 21.285us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 226 | 255 | 88.63 | |||
| V2 | random_reset | rv_timer_random_reset | 24.797m | 584.414ms | 41 | 50 | 82.00 |
| V2 | disabled | rv_timer_disabled | 5.471m | 217.327ms | 37 | 50 | 74.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 21.015m | 2.249s | 43 | 50 | 86.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 21.015m | 2.249s | 43 | 50 | 86.00 |
| V2 | stress | rv_timer_stress_all | 53.170m | 968.459ms | 42 | 50 | 84.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 33.738us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.120s | 179.313us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.120s | 179.313us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.700s | 67.350us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.670s | 34.589us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 21.285us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.790s | 134.591us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.700s | 67.350us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.670s | 34.589us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 21.285us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.790s | 134.591us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 253 | 290 | 87.24 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.970s | 156.825us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.290s | 499.622us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.290s | 499.622us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 19.922m | 646.827ms | 41 | 50 | 82.00 |
| V3 | TOTAL | 41 | 50 | 82.00 | |||
| TOTAL | 545 | 620 | 87.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 3 | 42.86 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.51 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 98.98 |
Exit reason: Error: User command failed Job returned non-zero exit code has 72 failures:
0.rv_timer_disabled.34774544546209381273812755760986535010078699543524959523142255365321831174537
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
[make]: simulate
cd /workspace/0.rv_timer_disabled/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836091273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2836091273
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.rv_timer_disabled.57833285423061224453141582547380810640099437478546641519595612362889836002666
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_disabled/latest/run.log
[make]: simulate
cd /workspace/2.rv_timer_disabled/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669313386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2669313386
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 9 more failures.
0.rv_timer_stress_all_with_rand_reset.48345941646383091279251330478560992066759853450658153412457553723034164594183
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/0.rv_timer_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539193863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2539193863
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
6.rv_timer_stress_all_with_rand_reset.92818842579134196943260304904395035762372408491308527935525157507920772391118
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/6.rv_timer_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147592910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.1147592910
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
2.rv_timer_cfg_update_on_fly.113153580199334664576350499594577977304744429676359137843832785503308694173768
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest/run.log
[make]: simulate
cd /workspace/2.rv_timer_cfg_update_on_fly/latest && /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474391624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.2474391624
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
9.rv_timer_cfg_update_on_fly.9738724524429511436996593997323785150039023050196877686188523510729589738729
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest/run.log
[make]: simulate
cd /workspace/9.rv_timer_cfg_update_on_fly/latest && /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283280105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.1283280105
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
3.rv_timer_random.90955311631619810543820896320748251367413108990325804896047189480433973244539
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_random/latest/run.log
[make]: simulate
cd /workspace/3.rv_timer_random/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265128571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4265128571
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
7.rv_timer_random.34767648197951716140973593533142241229163822951140008195751133081675305523654
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_random/latest/run.log
[make]: simulate
cd /workspace/7.rv_timer_random/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760500166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1760500166
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 27 more failures.
5.rv_timer_random_reset.51971598343973057826872125967893148134538279756143897702970811416856174030645
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_random_reset/latest/run.log
[make]: simulate
cd /workspace/5.rv_timer_random_reset/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504472885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1504472885
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
11.rv_timer_random_reset.1484379686226953852827143825653380771199891440243850091482090752884521344585
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_random_reset/latest/run.log
[make]: simulate
cd /workspace/11.rv_timer_random_reset/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607062601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2607062601
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
6.rv_timer_disabled.24560300038393759885627920418866559270277713044934912966091295376146210969656
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rv_timer_disabled.31883894013929026032275722169205597536894948061625045903154526178421019260891
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
20.rv_timer_stress_all_with_rand_reset.37521607319466666756241421442181020196086639089845470291998532169947387770504
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest/run.log
Job ID: smart:bc79a902-7dd4-48fc-87c4-b514e3e02901