RV_TIMER Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	33.696m	752.160ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	25.626us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	12.176us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.740s	850.942us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	121.076us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.990s	76.045us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	12.176us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	121.076us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	8.235m	315.704ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.958m	328.054ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	39.290m	10.000s	49	50	98.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	39.290m	10.000s	49	50	98.00
V2	stress	rv_timer_stress_all	1.497h	4.484s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.630s	16.797us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.490s	169.308us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.490s	169.308us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	25.626us	5	5	100.00
		rv_timer_csr_rw	0.610s	12.176us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	121.076us	5	5	100.00
		rv_timer_same_csr_outstanding	0.800s	164.335us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	25.626us	5	5	100.00
		rv_timer_csr_rw	0.610s	12.176us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	121.076us	5	5	100.00
		rv_timer_same_csr_outstanding	0.800s	164.335us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.910s	83.323us	5	5	100.00
		rv_timer_tl_intg_err	1.400s	119.519us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.400s	119.519us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	15.930m	528.529ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			582	620	93.87

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.59	99.36	98.73	100.00	--	100.00	100.00	99.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 34 failures:
- Test rv_timer_stress_all_with_rand_reset has 34 failures.
  - 1.rv_timer_stress_all_with_rand_reset.29707007765088973453961618444504235966118679365945397867324411869666465175925
    Line 401, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10572691822 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 10572691822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rv_timer_stress_all_with_rand_reset.101282165335013317100268784949217625949058260936438702438019772063516445285455
    Line 1060, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47670953127 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 47670953127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_ERROR (cip_base_vseq.sv:719) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 12.rv_timer_stress_all_with_rand_reset.91950665471333772795135304935023375414894199566929609042268077718453905705985
    Line 999, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 309649695733 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 309649695733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.rv_timer_stress_all_with_rand_reset.83812558217918721454727755543043152940137367869762939338349203497261656463939
    Line 744, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31814280635 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 31814280635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_disabled has 1 failures.
  - 33.rv_timer_disabled.34031888004587522934494661569631614824651071930389145629300830123877761441326
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_cfg_update_on_fly has 1 failures.
  - 49.rv_timer_cfg_update_on_fly.64061877867332013986115903599707000893984887735181519782791467073027258990400
    Line 273, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `df66f8a42e`