8faf04697a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 59.543m | 3.021s | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.660s | 20.219us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.640s | 13.930us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.910s | 291.420us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.820s | 158.042us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 3.350s | 207.132us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.640s | 13.930us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.820s | 158.042us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 37.418m | 261.808ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 5.613m | 206.354ms | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 26.698m | 1.828s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 26.698m | 1.828s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.194h | 1.710s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.640s | 45.042us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.570s | 185.371us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.570s | 185.371us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.660s | 20.219us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 13.930us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 158.042us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.900s | 81.156us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.660s | 20.219us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 13.930us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 158.042us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.900s | 81.156us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.990s | 289.163us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.350s | 424.647us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.350s | 424.647us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 23.376m | 420.329ms | 32 | 50 | 64.00 |
| V3 | TOTAL | 32 | 50 | 64.00 | |||
| TOTAL | 601 | 620 | 96.94 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.51 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 98.98 |
UVM_ERROR (cip_base_vseq.sv:756) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 12 failures:
0.rv_timer_stress_all_with_rand_reset.105675775455629564096153279257058468222743052513078305433599427331778276325982
Line 621, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43821330284 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 43821330284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_timer_stress_all_with_rand_reset.26118961322370286821944993399764123724219892234750943069173245004404306590432
Line 784, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55374566518 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 55374566518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (cip_base_vseq.sv:714) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 6 failures:
1.rv_timer_stress_all_with_rand_reset.43488675465719291995414352854693576304399448537630065649349362287971455639425
Line 362, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25982596063 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 25982596063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_timer_stress_all_with_rand_reset.3958215438860208956633478312975205144121101142604462367294205524585112710395
Line 1108, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 102736415054 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 102736415054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
47.rv_timer_random_reset.23139030316711971670723485814310559411528675394631326536001863986824975119218
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---