RV_TIMER Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	39.236m	174.877ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.610s	40.111us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.620s	15.140us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.570s	1.138ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.830s	284.126us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.470s	65.755us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.620s	15.140us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	284.126us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	26.010m	371.192ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.270m	170.489ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	19.871m	702.984ms	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	19.871m	702.984ms	50	50	100.00
V2	stress	rv_timer_stress_all	1.884h	2.563s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.610s	20.391us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.150s	1.040ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.150s	1.040ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.610s	40.111us	5	5	100.00
		rv_timer_csr_rw	0.620s	15.140us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	284.126us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	140.378us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.610s	40.111us	5	5	100.00
		rv_timer_csr_rw	0.620s	15.140us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	284.126us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	140.378us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.860s	87.525us	5	5	100.00
		rv_timer_tl_intg_err	1.370s	116.481us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.370s	116.481us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	23.764m	95.012ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			574	620	92.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.36	98.73	100.00	--	100.00	100.00	99.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 43 failures:
- Test rv_timer_stress_all_with_rand_reset has 43 failures.
  - 0.rv_timer_stress_all_with_rand_reset.78033970742002570666815748072539807207188971902224439724883360769966188744622
    Line 501, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30930919244 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30930919244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.64434762059084044751932472225582627190576107890947011857221324652261538257437
    Line 289, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17174122246 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10026 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17174122246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 41 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_disabled has 2 failures.
  - 11.rv_timer_disabled.62561004848112768877174406723030042892152467905148141615414222550983913691709
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.rv_timer_disabled.49912719654004972768409856565496746459178070791499919217275035266986176381545
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 143.rv_timer_random.90883821306031643309770995765763820026152021257294413368742432969800251245283
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/143.rv_timer_random/latest/run.log
```
  Job ID: smart:01a208d4-5819-4f28-b3f6-de4d42a0354b
```

RV_TIMER Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`