e4c5daa580| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 30.447m | 194.834ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.600s | 21.035us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 31.539us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.420s | 1.089ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.770s | 27.525us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.110s | 24.697us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 31.539us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.770s | 27.525us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 18.757m | 575.192ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.984m | 185.971ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 23.088m | 1.764s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 23.088m | 1.764s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 58.236m | 1.198s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 17.807us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.950s | 143.572us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.950s | 143.572us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.600s | 21.035us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 31.539us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.770s | 27.525us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.830s | 141.703us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.600s | 21.035us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 31.539us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.770s | 27.525us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.830s | 141.703us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.050s | 216.052us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.420s | 109.313us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.420s | 109.313us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 25.285m | 259.817ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
1.rv_timer_stress_all_with_rand_reset.70493628513851192845311466070872079758656232651433712432155316791201809887308
Line 621, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 245595346217 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 245595346217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_timer_stress_all_with_rand_reset.23242188622624489660788037906025277930753476433343909457511338078378384556031
Line 285, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3948098646 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3948098646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
10.rv_timer_disabled.99799199913129141249773698907173658402987327438788358222902840875694307040709
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_timer_disabled.95781701772446392359037415687717145634285188842597813579431615461387353235355
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---