5fd4ecc0fc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 44.626m | 130.492ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 26.177us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.610s | 24.513us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.530s | 1.101ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.790s | 104.940us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.720s | 36.922us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.610s | 24.513us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.790s | 104.940us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 20.181m | 39.809ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.570m | 839.796ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 40.201m | 5.973s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 40.201m | 5.973s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.326h | 4.636s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.690s | 167.542us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.250s | 623.598us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.250s | 623.598us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 26.177us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 24.513us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 104.940us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.940s | 47.481us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 26.177us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 24.513us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 104.940us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.940s | 47.481us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.020s | 381.600us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.360s | 132.776us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.360s | 132.776us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 21.209m | 118.314ms | 14 | 50 | 28.00 |
| V3 | TOTAL | 14 | 50 | 28.00 | |||
| TOTAL | 582 | 620 | 93.87 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
0.rv_timer_stress_all_with_rand_reset.32811711673065240193517780420930164036198437828433472664586992365255437806500
Line 797, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 107148672331 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107148672331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_timer_stress_all_with_rand_reset.88413682940099835980974009618185066247858697969464676015977840816711198458092
Line 496, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 67654355967 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 67654355967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
5.rv_timer_disabled.49055093587970312750155245217470663359949962826185012424711001337951778872212
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_timer_disabled.35257094016815613524918720117135191806090889633529412902576817073859818357953
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---