RV_TIMER Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	57.041m	619.481ms	198	200	99.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.880s	16.027us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.890s	169.050us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.870s	3.084ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.190s	154.610us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.410s	38.816us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.890s	169.050us	20	20	100.00
		rv_timer_csr_aliasing	1.190s	154.610us	5	5	100.00
V1		TOTAL			253	255	99.22
V2	random_reset	rv_timer_random_reset	27.456m	355.836ms	50	50	100.00
V2	disabled	rv_timer_disabled	8.233m	227.485ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	30.736m	687.567ms	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	30.736m	687.567ms	50	50	100.00
V2	stress	rv_timer_stress_all	1.363h	488.316ms	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.880s	57.699us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.790s	990.124us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.790s	990.124us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.880s	16.027us	5	5	100.00
		rv_timer_csr_rw	0.890s	169.050us	20	20	100.00
		rv_timer_csr_aliasing	1.190s	154.610us	5	5	100.00
		rv_timer_same_csr_outstanding	1.240s	37.471us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.880s	16.027us	5	5	100.00
		rv_timer_csr_rw	0.890s	169.050us	20	20	100.00
		rv_timer_csr_aliasing	1.190s	154.610us	5	5	100.00
		rv_timer_same_csr_outstanding	1.240s	37.471us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	1.030s	172.510us	5	5	100.00
		rv_timer_tl_intg_err	2.220s	130.605us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.220s	130.605us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.253m	6.823ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			578	620	93.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.36	99.04	100.00	--	100.00	100.00	99.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test rv_timer_stress_all_with_rand_reset has 37 failures.
  - 1.rv_timer_stress_all_with_rand_reset.104505271209010642535011731198040117588624666992426657489110418954167112848201
    Line 117, in log /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8119540789 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8119540789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rv_timer_stress_all_with_rand_reset.49910000878396075974956689305440881267441071095956072179874979495904189016216
    Line 113, in log /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1840056985 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1840056985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
Job timed out after * minutes has 2 failures:
- Test rv_timer_random has 2 failures.
  - 0.rv_timer_random.28822790110037317544076382147638207860176714874534141004722347222765266508036
    Log /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_random/latest/run.log
```
  Job timed out after 60 minutes
```
  - 40.rv_timer_random.68418331273175212965588073188742361013717664657466130805490500143842083620633
    Log /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/40.rv_timer_random/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_disabled has 2 failures.
  - 23.rv_timer_disabled.97473282829120433931758813515634504696140300783264481025771094341700238333043
    Line 67, in log /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/23.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.rv_timer_disabled.100985539295847208208105197994775061476507882000213860498728557587088351233987
    Line 64, in log /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/24.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 20.rv_timer_stress_all_with_rand_reset.43886636260103465100189181833385057975765219666014373155794246867501336273626
    Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1127420959 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1127420959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a861deb3de`