RV_TIMER Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	52.696m	116.538ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.740s	186.263us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.720s	32.076us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.140s	412.043us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.980s	33.299us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.830s	144.598us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.720s	32.076us	20	20	100.00
		rv_timer_csr_aliasing	0.980s	33.299us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	23.899m	157.153ms	49	50	98.00
V2	disabled	rv_timer_disabled	9.161m	196.412ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	37.431m	7.850s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	37.431m	7.850s	50	50	100.00
V2	stress	rv_timer_stress_all	1.874h	4.295s	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.710s	14.626us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.850s	379.897us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.850s	379.897us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.740s	186.263us	5	5	100.00
		rv_timer_csr_rw	0.720s	32.076us	20	20	100.00
		rv_timer_csr_aliasing	0.980s	33.299us	5	5	100.00
		rv_timer_same_csr_outstanding	0.980s	20.365us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.740s	186.263us	5	5	100.00
		rv_timer_csr_rw	0.720s	32.076us	20	20	100.00
		rv_timer_csr_aliasing	0.980s	33.299us	5	5	100.00
		rv_timer_same_csr_outstanding	0.980s	20.365us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	1.050s	961.233us	5	5	100.00
		rv_timer_tl_intg_err	1.760s	295.188us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.760s	295.188us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.328m	7.207ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			579	620	93.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.70	99.36	99.04	100.00	--	100.00	100.00	99.77

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test rv_timer_stress_all_with_rand_reset has 36 failures.
  - 1.rv_timer_stress_all_with_rand_reset.106281786696661852124296853194227997653799029698416132215655437599571292419679
    Line 204, in log /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5151911518 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5151911518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rv_timer_stress_all_with_rand_reset.82072484680625831069883802663339253766173132413655808958928066625992828779809
    Line 80, in log /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 481246078 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 481246078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_timer_random_reset has 1 failures.
  - 4.rv_timer_random_reset.6607095968579409931250503750206771813844503173351656028133380538371347776762
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_disabled has 2 failures.
  - 13.rv_timer_disabled.87878540206871863358930211611494581028818327723364420577375596755016077408468
    Line 64, in log /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.rv_timer_disabled.101751440139359351094425752163262552144439254082937806803337277980762200074464
    Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/24.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_stress_all has 1 failures.
  - 18.rv_timer_stress_all.7605425246478527602293819672104893519098769579349544879631047419624899893221
    Line 96, in log /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 7.rv_timer_stress_all_with_rand_reset.73584536341141677628604282889987663804519580443085542525100884529278832441957
    Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153403900 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 153403900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`