SPI_DEVICE Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.340s	51.944us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	41.202us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.000s	251.464us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.060s	3.019ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	28.340s	1.504ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.480s	80.243us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.000s	251.464us	20	20	100.00
		spi_device_csr_aliasing	28.340s	1.504ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	15.830s	988.793us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	5.660s	643.576us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	25.980m	62.655ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	52.798m	123.690ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	41.081m	120.232ms	48	50	96.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	43.038m	213.874ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	43.038m	213.874ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.830s	53.654us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.930s	414.758us	50	50	100.00
V2	interrupts	spi_device_intr	2.218m	73.602ms	50	50	100.00
V2	abort	spi_device_abort	0.800s	38.466us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.770s	337.775us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.430s	991.352us	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.360s	1.457ms	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.137h	84.754ms	50	50	100.00
V2	perf	spi_device_perf	48.083m	171.627ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.860s	36.865us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.080s	113.050us	19	20	95.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	18.387us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	5.800s	497.335us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.800s	497.335us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.360s	39.720ms	50	50	100.00
		spi_device_tpm_sts_read	1.160s	189.387us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.519m	38.645ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	39.630s	65.488ms	50	50	100.00
		spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	57.610s	91.208ms	50	50	100.00
		spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	57.610s	91.208ms	50	50	100.00
		spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	16.530s	5.478ms	50	50	100.00
		spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	16.530s	5.478ms	50	50	100.00
		spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	16.530s	5.478ms	50	50	100.00
		spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	16.530s	5.478ms	50	50	100.00
		spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.002m	21.721ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	48.890s	81.109ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	48.890s	81.109ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	48.890s	81.109ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.265m	16.845ms	49	50	98.00
		spi_device_read_buffer_direct	8.650s	2.303ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	48.890s	81.109ms	50	50	100.00
		spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.371m	477.687ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.550s	8.007ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.550s	8.007ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.818m	269.128ms	44	50	88.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.637m	107.128ms	48	50	96.00
V2	stress_all	spi_device_stress_all	1.579h	488.810ms	15	50	30.00
V2	alert_test	spi_device_alert_test	0.780s	15.081us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	11.143us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.300s	1.071ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.300s	1.071ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	41.202us	5	5	100.00
		spi_device_csr_rw	3.000s	251.464us	20	20	100.00
		spi_device_csr_aliasing	28.340s	1.504ms	5	5	100.00
		spi_device_same_csr_outstanding	4.680s	2.827ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	41.202us	5	5	100.00
		spi_device_csr_rw	3.000s	251.464us	20	20	100.00
		spi_device_csr_aliasing	28.340s	1.504ms	5	5	100.00
		spi_device_same_csr_outstanding	4.680s	2.827ms	20	20	100.00
V2		TOTAL			1633	1680	97.20
V2S	tl_intg_err	spi_device_sec_cm	1.380s	385.978us	5	5	100.00
		spi_device_tl_intg_err	22.970s	16.359ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.970s	16.359ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1773	1820	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	30	83.33
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.91	99.00	96.26	98.63	92.06	97.93	96.16	98.30

Failure Buckets

UVM_ERROR (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 27 failures:

Test spi_device_stress_all has 27 failures.

0.spi_device_stress_all.3108507632
Line 219, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1477371231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x2 [10] vs 0xfe [11111110]) addr 0xa5e9178 read out mismatch
  UVM_ERROR @ 1477371231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xc5 [11000101] vs 0x40 [1000000]) addr 0xa5e9179 read out mismatch
  UVM_ERROR @ 1477371231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xf6 [11110110] vs 0xef [11101111]) addr 0xa5e917a read out mismatch
  UVM_ERROR @ 1477371231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x74 [1110100] vs 0x12 [10010]) addr 0xa5e917b read out mismatch
  UVM_ERROR @ 1485591231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xe2 [11100010] vs 0x66 [1100110]) addr 0xa5e917c read out mismatch

2.spi_device_stress_all.1494917703
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 37767713683 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x72 [1110010] vs 0xd [1101]) addr 0x901ff288 read out mismatch
  UVM_ERROR @ 37767713683 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xc1 [11000001] vs 0xbd [10111101]) addr 0x901ff289 read out mismatch
  UVM_ERROR @ 37767713683 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x44 [1000100] vs 0x98 [10011000]) addr 0x901ff28a read out mismatch
  UVM_ERROR @ 37767713683 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x27 [100111] vs 0xb2 [10110010]) addr 0x901ff28b read out mismatch
  UVM_ERROR @ 37770083683 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x87 [10000111] vs 0xb9 [10111001]) addr 0x901ff28c read out mismatch

... and 25 more failures.

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 8 failures:

Test spi_device_flash_and_tpm has 6 failures.

4.spi_device_flash_and_tpm.1161573567
Line 247, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 8058676286 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 8058676286 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 8058676286 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 8058676286 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 8058676286 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

6.spi_device_flash_and_tpm.3692461578
Line 217, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 499778816 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 499778816 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 499778816 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 499778816 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 499778816 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

... and 4 more failures.

Test spi_device_flash_and_tpm_min_idle has 2 failures.

29.spi_device_flash_and_tpm_min_idle.4152446294
Line 238, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 10840920077 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 10840920077 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 10840920077 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 10840920077 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 10840920077 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

31.spi_device_flash_and_tpm_min_idle.2603269456
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 242595624854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 242595624854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 242595624854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 242595624854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 242595624854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes:: has 3 failures:

Test spi_device_stress_all has 3 failures.

8.spi_device_stress_all.2647274246
Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1341411821248 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 2508 [0x9cc]) get_sram_space_bytes::
  UVM_ERROR @ 1341413125588 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2709674659 [0xa1825aa3] vs 3749494952 [0xdf7cc0a8]) Compare SPI RX data, addr: 0x30
  UVM_ERROR @ 1341413690802 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (82865131 [0x4f06beb] vs 1582417583 [0x5e51c6af]) Compare SPI RX data, addr: 0x34
  UVM_ERROR @ 1341414256016 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (182751506 [0xae49112] vs 388226058 [0x1723dc0a]) Compare SPI RX data, addr: 0x38
  UVM_ERROR @ 1341414864708 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (4237681770 [0xfc95e46a] vs 2956212946 [0xb0343ad2]) Compare SPI RX data, addr: 0x3c

24.spi_device_stress_all.2548464576
Line 319, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 54707308140 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 1612 [0x64c]) get_sram_space_bytes::
  UVM_ERROR @ 54708558150 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 1616 [0x650]) get_sram_space_bytes::
  UVM_ERROR @ 54739818368 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2667582073 [0x9f001279] vs 584682913 [0x22d98da1]) Compare SPI TX data
  UVM_ERROR @ 54755891862 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (16 [0x10] vs 1512 [0x5e8]) get_sram_filled_bytes
  UVM_ERROR @ 54756308532 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2719642179 [0xa21a7243] vs 1652810963 [0x6283e4d3]) Compare SPI RX data, addr: 0x5e8

... and 1 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1243) [scoreboard] Check failed data_act == data_exp (* [*] vs * [*]) Compare SPI TX data has 2 failures:

Test spi_device_stress_all has 2 failures.

18.spi_device_stress_all.1700480936
Line 235, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1068031476528 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (3756857047 [0xdfed16d7] vs 2405893941 [0x8f670735]) Compare SPI TX data
  UVM_ERROR @ 1068064474528 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (3954363710 [0xebb2cd3e] vs 3127950313 [0xba70bbe9]) Compare SPI TX data
  UVM_ERROR @ 1068074776528 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xdb [11011011] vs 0xec [11101100]) addr 0x268b97d4 read out mismatch
  UVM_ERROR @ 1068074776528 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x9 [1001] vs 0xf5 [11110101]) addr 0x268b97d5 read out mismatch
  UVM_ERROR @ 1068074776528 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xa0 [10100000] vs 0xb8 [10111000]) addr 0x268b97d6 read out mismatch

40.spi_device_stress_all.3214664681
Line 228, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 66253663529 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (677433107 [0x2860cf13] vs 3225170140 [0xc03c30dc]) Compare SPI TX data
  UVM_ERROR @ 66254894313 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (4156238907 [0xf7bb2c3b] vs 2305120358 [0x89655866]) Compare SPI TX data
  UVM_ERROR @ 66256125097 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (848267659 [0x328f898b] vs 444879657 [0x1a845329]) Compare SPI TX data
  UVM_ERROR @ 66257355881 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (4090754172 [0xf3d3f47c] vs 619596599 [0x24ee4b37]) Compare SPI TX data
  UVM_ERROR @ 66258586665 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (3523201972 [0xd1ffcbb4] vs 2334075434 [0x8b1f2a2a]) Compare SPI TX data

Offending '(!dst_pulse_o)' has 1 failures:

Test spi_device_fifo_underflow_overflow has 1 failures.

0.spi_device_fifo_underflow_overflow.2464019262
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 15522646526 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 31468876098ps failed at 31468911812ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 31468911812 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

UVM_ERROR (cip_base_vseq.sv:245) [spi_device_mem_parity_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

Test spi_device_mem_parity has 1 failures.

10.spi_device_mem_parity.1862098663
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4610287 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x44 read out mismatch
  UVM_ERROR @   4610287 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000044
  UVM_ERROR @   4776955 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x44 read out mismatch
  UVM_ERROR @   4776955 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000047
  UVM_ERROR @   4943623 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x44 read out mismatch

UVM_ERROR (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes has 1 failures:

Test spi_device_stress_all has 1 failures.

10.spi_device_stress_all.855608449
Line 230, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 89188176563 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 344 [0x158]) get_sram_filled_bytes
  UVM_ERROR @ 89188219117 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3619147761 [0xd7b7cff1] vs 2925221347 [0xae5b55e3]) Compare SPI RX data, addr: 0x158
  UVM_ERROR @ 89188282948 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (374599193 [0x1653ee19] vs 2048878884 [0x7a1f6924]) Compare SPI RX data, addr: 0x15c
  UVM_ERROR @ 89188325502 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (653214810 [0x26ef445a] vs 1817311161 [0x6c51f7b9]) Compare SPI RX data, addr: 0x160
  UVM_ERROR @ 89188538272 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3282251473 [0xc3a32ed1] vs 3451219803 [0xcdb56f5b]) Compare SPI RX data, addr: 0x164

Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 12.spi_device_stress_all.681208485
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_stress_all/latest/run.log
```
  Job ID: smart:50570c44-6044-40fd-be33-15a4a4b88d34
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_fifo_underflow_overflow has 1 failures.
  - 37.spi_device_fifo_underflow_overflow.2773525598
    Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 47.spi_device_flash_mode.3832151701
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 565191251 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 668472513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 1 failures:

Test spi_device_stress_all has 1 failures.

48.spi_device_stress_all.372000314
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 123025499454 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 124877899454 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 125120179454 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 127773706455 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xb [1011] vs 0x49 [1001001]) addr 0x3278d92e read out mismatch
  UVM_ERROR @ 127773706455 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x7 [111] vs 0x98 [10011000]) addr 0x3278d92f read out mismatch