SPI_DEVICE Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: `748235cbb6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.400s	352.248us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.480s	244.661us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.840s	126.164us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.070s	11.897ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	28.040s	5.531ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.390s	148.466us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.840s	126.164us	20	20	100.00
		spi_device_csr_aliasing	28.040s	5.531ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	15.760s	1.393ms	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	7.110s	936.404us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	24.296m	68.813ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	53.049m	55.972ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	35.530m	180.368ms	47	50	94.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	53.330m	131.033ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	53.330m	131.033ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.880s	17.964us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.990s	47.270us	48	50	96.00
V2	interrupts	spi_device_intr	2.417m	38.672ms	50	50	100.00
V2	abort	spi_device_abort	0.800s	17.028us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.850s	388.942us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.360s	1.681ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.330s	362.923us	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	48.794m	438.557ms	50	50	100.00
V2	perf	spi_device_perf	49.518m	90.862ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.840s	23.228us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	33.928us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	16.029us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	11.020s	422.712us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.020s	422.712us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	40.400s	13.201ms	50	50	100.00
		spi_device_tpm_sts_read	1.240s	689.391us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.096m	33.640ms	49	50	98.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.004m	97.149ms	50	50	100.00
		spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	55.380s	59.689ms	50	50	100.00
		spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	55.380s	59.689ms	50	50	100.00
		spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	cmd_info_slots	spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	cmd_read_status	spi_device_intercept	13.100s	13.371ms	50	50	100.00
		spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	cmd_read_jedec	spi_device_intercept	13.100s	13.371ms	50	50	100.00
		spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	cmd_read_sfdp	spi_device_intercept	13.100s	13.371ms	50	50	100.00
		spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	cmd_fast_read	spi_device_intercept	13.100s	13.371ms	50	50	100.00
		spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	flash_cmd_upload	spi_device_upload	1.196m	77.766ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	52.160s	63.887ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	52.160s	63.887ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	52.160s	63.887ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.177m	13.540ms	49	50	98.00
		spi_device_read_buffer_direct	8.710s	6.381ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	52.160s	63.887ms	50	50	100.00
		spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	quad_spi	spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	dual_spi	spi_device_flash_all	8.554m	106.494ms	43	50	86.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.140s	18.814ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.140s	18.814ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.277m	113.915ms	41	50	82.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.210m	612.697ms	48	50	96.00
V2	stress_all	spi_device_stress_all	2.667h	523.194ms	37	50	74.00
V2	alert_test	spi_device_alert_test	0.780s	34.992us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	52.740us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.940s	4.293ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.940s	4.293ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.480s	244.661us	5	5	100.00
		spi_device_csr_rw	2.840s	126.164us	20	20	100.00
		spi_device_csr_aliasing	28.040s	5.531ms	5	5	100.00
		spi_device_same_csr_outstanding	4.760s	1.056ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.480s	244.661us	5	5	100.00
		spi_device_csr_rw	2.840s	126.164us	20	20	100.00
		spi_device_csr_aliasing	28.040s	5.531ms	5	5	100.00
		spi_device_same_csr_outstanding	4.760s	1.056ms	20	20	100.00
V2		TOTAL			1642	1680	97.74
V2S	tl_intg_err	spi_device_sec_cm	1.200s	314.255us	5	5	100.00
		spi_device_tl_intg_err	23.300s	12.090ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.300s	12.090ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1782	1820	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	28	77.78
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.11	99.02	96.33	98.63	92.06	98.07	95.86	99.76

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 12 failures:

Test spi_device_stress_all has 4 failures.

1.spi_device_stress_all.63712572994263706432204167125947946915997248171412934988811687790760983302898
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 26797212776 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 38479227415 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/9
  UVM_INFO @ 43717164042 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/18
  UVM_INFO @ 52903543307 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 4/9
  UVM_INFO @ 53640613659 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/18

5.spi_device_stress_all.17515246402550526760323455688964686660199767764153702768192837671802873504252
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 100551603971 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 101234060041 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 101850665889 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/14
  UVM_INFO @ 101858972843 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/6
  UVM_INFO @ 104133754681 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/14

... and 2 more failures.

Test spi_device_flash_and_tpm has 4 failures.

14.spi_device_flash_and_tpm.110888613047485591413696315871179153211583131212408281646014988910087777140055
Line 266, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 119204599286 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 121583019798 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 121619671752 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 122543187950 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 122737099830 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0

33.spi_device_flash_and_tpm.815046833718191999806164399830621256051102643926786264316298841409899879387
Line 267, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 27137457475 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 29652478171 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/18
  UVM_INFO @ 32564077327 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 9/14
  UVM_INFO @ 32712233379 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/18
  UVM_INFO @ 36101842043 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 13/18

... and 2 more failures.

Test spi_device_flash_and_tpm_min_idle has 2 failures.

17.spi_device_flash_and_tpm_min_idle.99598046711883210631456395021618779143759270910964576179365080006254685211120
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1467922461 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 1889347664 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/11
  UVM_INFO @ 2022356250 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 5/16
  UVM_INFO @ 2435959856 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/11
  UVM_INFO @ 2970436110 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 6/16

33.spi_device_flash_and_tpm_min_idle.34836598687943913745995467573902830970769071571692369087910796215674591570227
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1413843101 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 1564523713 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/17
  UVM_INFO @ 2059856861 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 4/15
  UVM_INFO @ 2573113229 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/17
  UVM_INFO @ 2729809997 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 5/15

Test spi_device_flash_all has 2 failures.

27.spi_device_flash_all.61571169279573010274696572332572632758872942037978752493378884423523699173166
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 2344250479 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 2443950697 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/14
  UVM_INFO @ 2770000479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.spi_device_flash_all.24271560411468600168440370969321974820699228998615383148482659416490030532211
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 6001867749 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 6483447749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_base_vseq.sv:413) [spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail has 3 failures:
- Test spi_device_stress_all has 3 failures.
  - 15.spi_device_stress_all.2875765110604595282068849079745230583602424571139754615681766366014605361862
    Line 344, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 523194237673 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 523194237673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.spi_device_stress_all.102591752582317731623158623353806002455352029483161277368515962738305596919788
    Line 426, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 76314097709 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 76314097709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (spi_device_scoreboard.sv:497) scoreboard [scoreboard] flash_status mismatch, backdoor value: *, exp: * has 3 failures:

Test spi_device_flash_all has 3 failures.

19.spi_device_flash_all.54172643503823355615504937325668031523628016231461372682592945223583873297034
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 235389927750 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x9d28a6, exp: 0xb00bba
  UVM_ERROR @ 235389927750 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x9d28a6, exp: 0xb00bba
  UVM_INFO @ 235401584340 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/20
  UVM_INFO @ 251253228820 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/20
  UVM_INFO @ 258835493145 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 11/20

25.spi_device_flash_all.36756429932963890393340108572418183969398084772501392208885033593563109150591
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 27939752107 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x94047a, exp: 0x992674
  UVM_ERROR @ 27939752107 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x94047a, exp: 0x992674
  UVM_INFO @ 29348616472 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/16
  UVM_INFO @ 30847994572 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/16
  UVM_INFO @ 33239381420 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 11/16

... and 1 more failures.

Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test spi_device_stress_all has 3 failures.
  - 19.spi_device_stress_all.41290006278509146052477122311637669410767335900212121331073023405406685575424
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_stress_all/latest/run.log
```
  Job ID: smart:82380d9c-b7d8-4d51-baed-4cbda0bba793
```
  - 25.spi_device_stress_all.63161887490616478393101987302554219795617635388157650370148040208241090892204
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_stress_all/latest/run.log
```
  Job ID: smart:3647702e-b70e-411f-a2da-b8dc4524d005
```
  - ... and 1 more failures.

UVM_ERROR (spi_device_scoreboard.sv:436) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 2 failures:

Test spi_device_flash_and_tpm has 1 failures.

2.spi_device_flash_and_tpm.101852698789880819673219761645519640381299707229376568660552343619083834911736
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 14424670718 ps: (spi_device_scoreboard.sv:436) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 3, act: 0x27, exp: '{'hff}
  UVM_FATAL @ 14498811343 ps: (spi_device_scoreboard.sv:1165) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 14498811343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_tpm_all has 1 failures.

26.spi_device_tpm_all.38718017759835492498478768664244679444186056749407852603390305584833938618833
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_tpm_all/latest/run.log

  UVM_ERROR @ 704494772 ps: (spi_device_scoreboard.sv:436) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0x36c0815a, exp: '{'hffffffff}
  UVM_FATAL @ 705020418 ps: (spi_device_scoreboard.sv:1165) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 705020418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (spi_device_scoreboard.sv:263) [scoreboard] Check failed tpm_read_sw_q.size == * (* [*] vs * [*]) has 2 failures:

Test spi_device_stress_all has 1 failures.

20.spi_device_stress_all.20452401740703819168157538667415678481616356265671955032195060479148077116611
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/20.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1033269033 ps: (spi_device_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1033269033 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @212726 : rhs = @0
  
  Error-[NOA] Null object access
  ../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 309

Test spi_device_flash_and_tpm has 1 failures.

38.spi_device_flash_and_tpm.48489669053895537815039975238977760473160231815281157468740043888504015927111
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/38.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 1991990649 ps: (spi_device_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1991990649 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @312651 : rhs = @0
  
  Error-[NOA] Null object access
  ../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 309

UVM_ERROR (spi_device_env_pkg.sv:189) [scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes has 1 failures:

Test spi_device_rx_async_fifo_reset has 1 failures.

2.spi_device_rx_async_fifo_reset.89015404566001615301487697862020129284472844712437857286959317657482094473796
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_rx_async_fifo_reset/latest/run.log

  UVM_ERROR @   5221133 ps: (spi_device_env_pkg.sv:189) [uvm_test_top.env.scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (0 [0x0] vs 8 [0x8]) get_sram_filled_bytes
  UVM_ERROR @   8194093 ps: (spi_device_env_pkg.sv:189) [uvm_test_top.env.scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (0 [0x0] vs 8 [0x8]) get_sram_filled_bytes
  UVM_ERROR @  26591482 ps: (spi_device_env_pkg.sv:189) [uvm_test_top.env.scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (0 [0x0] vs 8 [0x8]) get_sram_filled_bytes
  UVM_ERROR @  29554442 ps: (spi_device_env_pkg.sv:189) [uvm_test_top.env.scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (0 [0x0] vs 8 [0x8]) get_sram_filled_bytes
  Starting assertion attempts at time 42719541ps: level = 0 arg = tb.dut.u_txf_underflow.SrcPulseCheck_M (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:457))

UVM_ERROR (spi_device_scoreboard.sv:1257) [scoreboard] Check failed data_act == data_exp (* [*] vs * [*]) Compare SPI TX data has 1 failures:

Test spi_device_fifo_underflow_overflow has 1 failures.

4.spi_device_fifo_underflow_overflow.47607730843429579393580112438167221247007582104223366763743606974243288735346
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_fifo_underflow_overflow/latest/run.log

  UVM_ERROR @ 8537993253 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (1669939264 [0x63894040] vs 1080265024 [0x40638940]) Compare SPI TX data
  UVM_ERROR @ 8538344253 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (1773205056 [0x69b0f640] vs 3832131830 [0xe469b0f6]) Compare SPI TX data
  UVM_ERROR @ 8542607253 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (1208947940 [0x480f14e4] vs 1967656724 [0x75480f14]) Compare SPI TX data
  UVM_ERROR @ 8543779253 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (3714165877 [0xdd61ac75] vs 2564645292 [0x98dd61ac]) Compare SPI TX data
  Starting assertion attempts at time 11501516253ps: level = 0 arg = tb.dut.u_txf_underflow.SrcPulseCheck_M (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:457))

UVM_ERROR (spi_device_pass_base_vseq.sv:641) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

5.spi_device_flash_all.98124515854383274843203248898949176948422661668874420875648795233528143233103
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 2592235574 ps: (spi_device_pass_base_vseq.sv:641) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 4209475574 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/20
  UVM_INFO @ 5903064574 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/20
  UVM_INFO @ 7552967574 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/20
  UVM_INFO @ 9964129574 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/20

UVM_ERROR (spi_monitor.sv:323) [monitor] Check failed data[i] !== *'bz (z [0xz] vs z [0xz]) has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

13.spi_device_flash_and_tpm.32694251056751447449152413546222693665965780478510540604476154713564564960224
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/13.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 46035426503 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])
  UVM_ERROR @ 46035426503 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])
  UVM_ERROR @ 46035426503 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])
  UVM_ERROR @ 46035426503 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])
  UVM_ERROR @ 46035426503 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])

UVM_ERROR (spi_device_pass_base_vseq.sv:641) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

23.spi_device_flash_and_tpm.5705033957461619866704809644927801250903724327510926113320762148936062234310
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 17385926648 ps: (spi_device_pass_base_vseq.sv:641) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 17409246648 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/17
  UVM_INFO @ 18142641648 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/17
  UVM_INFO @ 19170175648 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/17
  UVM_INFO @ 21256753648 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/17

UVM_ERROR (spi_device_scoreboard.sv:1395) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_rx_async_fifo_reset has 1 failures.
  - 24.spi_device_rx_async_fifo_reset.15967101609793854322708016288175469246551991819794624241240134023708114068510
    Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @  42754207 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @  42754207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 24.spi_device_flash_mode.113531083654267063877321014548838722679335587389819650546049381768487868623269
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 224051441 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 1158706261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:

Test spi_device_stress_all has 1 failures.

31.spi_device_stress_all.34629879545516954913144892017414740893190147710155936481751034736406912533143
Line 366, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 411958841125 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 411959233979 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 411978162399 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 411986840901 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 411988090891 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0

UVM_ERROR (spi_device_scoreboard.sv:985) [scoreboard] Check failed item.d_data == data_exp (* [*] vs * [*]) Compare SPI RX data, addr: * has 1 failures:

Test spi_device_fifo_underflow_overflow has 1 failures.

40.spi_device_fifo_underflow_overflow.52419930579534656262631541572828200604228112284385198602920460084825910864894
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_fifo_underflow_overflow/latest/run.log

  UVM_ERROR @ 5222656282 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2429228139 [0x90cb146b] vs 3407113197 [0xcb146bed]) Compare SPI RX data, addr: 0x16c
  UVM_ERROR @ 5222812537 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3842030231 [0xe500ba97] vs 12228496 [0xba9790]) Compare SPI RX data, addr: 0x170
  UVM_ERROR @ 5222958375 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3617801015 [0xd7a34337] vs 2739091429 [0xa34337e5]) Compare SPI RX data, addr: 0x174
  UVM_ERROR @ 5223052128 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3367271363 [0xc8b47bc3] vs 3028009943 [0xb47bc3d7]) Compare SPI RX data, addr: 0x178
  UVM_ERROR @ 5223166715 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3180153402 [0xbd8d4a3a] vs 2370452168 [0x8d4a3ac8]) Compare SPI RX data, addr: 0x17c

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_fifo_underflow_overflow has 1 failures.
  - 43.spi_device_fifo_underflow_overflow.58136418386881866287133481593357669501768783800251634856792747921957184868331
    Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/43.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

44.spi_device_flash_and_tpm.5873581090503961926248264406344880367889804916900279979127275995128223478304
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 16632396609 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed
  UVM_INFO @ 18595716609 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/18
  UVM_INFO @ 20529156609 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/18
  UVM_INFO @ 21229556609 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 9/18
  UVM_INFO @ 22123436609 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 10/18

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_all has 1 failures.

47.spi_device_flash_all.58191745351985029974748469282070531493433308061457221017372261789626539663993
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 8345898804 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4d33ec) != exp '{'{other_status:'h1885c7, wel:'h1, busy:'h0}, '{other_status:'hdabab, wel:'h1, busy:'h0}}
  UVM_INFO @ 18853181804 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/9
  UVM_INFO @ 24652698804 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/9
  UVM_INFO @ 27723892804 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/9
  UVM_INFO @ 32917139804 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/9

UVM_ERROR (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes has 1 failures:

Test spi_device_stress_all has 1 failures.

49.spi_device_stress_all.54983919350829558108676028820852795901848724829868178121707399475711957969523
Line 299, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/49.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 359807480345 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 96 [0x60]) get_sram_filled_bytes
  UVM_ERROR @ 359808229345 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2917684505 [0xade85519] vs 263465980 [0xfb42bfc]) Compare SPI TX data
  UVM_ERROR @ 359816020345 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (1715565570 [0x66417402] vs 23790484 [0x16b0394]) Compare SPI TX data
  UVM_ERROR @ 359825921345 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2359765007 [0x8ca7280f] vs 1904875134 [0x718a167e]) Compare SPI TX data
  UVM_ERROR @ 359833864345 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (467767467 [0x1be190ab] vs 2920368956 [0xae114b3c]) Compare SPI TX data