919341eb22| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 1.238m | 77.017ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.370s | 45.506us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.760s | 372.560us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 38.130s | 3.506ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 21.890s | 330.002us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.890s | 217.663us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.760s | 372.560us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 21.890s | 330.002us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.680s | 22.094us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.800s | 96.331us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.860s | 79.415us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.750s | 6.664us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.810s | 62.340us | 20 | 20 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 21.330s | 1.813ms | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 21.330s | 1.813ms | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 37.930s | 19.802ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.210s | 161.467us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.180m | 11.947ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 54.720s | 43.065ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 42.330s | 16.659ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 42.330s | 16.659ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 35.850s | 52.057ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 35.850s | 52.057ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 35.850s | 52.057ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 35.850s | 52.057ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 35.850s | 52.057ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 43.630s | 26.031ms | 38 | 50 | 76.00 |
| V2 | mailbox_command | spi_device_mailbox | 5.747m | 337.423ms | 43 | 50 | 86.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 5.747m | 337.423ms | 43 | 50 | 86.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 5.747m | 337.423ms | 43 | 50 | 86.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 1.990m | 7.945ms | 43 | 50 | 86.00 |
| spi_device_read_buffer_direct | 21.020s | 1.477ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 5.747m | 337.423ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 7.350s | 589.807us | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 25.020s | 9.221ms | 22 | 50 | 44.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 25.020s | 9.221ms | 22 | 50 | 44.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 1.238m | 77.017ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 1.037m | 5.981ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 9.640s | 758.754us | 12 | 50 | 24.00 |
| V2 | alert_test | spi_device_alert_test | 0.790s | 65.551us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.780s | 18.699us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.830s | 871.819us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.830s | 871.819us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.370s | 45.506us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.760s | 372.560us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 21.890s | 330.002us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.070s | 221.303us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.370s | 45.506us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.760s | 372.560us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 21.890s | 330.002us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.070s | 221.303us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 760 | 980 | 77.55 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.100s | 84.099us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 22.240s | 15.803ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.240s | 15.803ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 850 | 1120 | 75.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.16 | 97.62 | 92.91 | 98.61 | 80.85 | 95.99 | 90.96 | 88.18 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 212 failures:
0.spi_device_cfg_cmd.96612941422538230974392367918872322694952169508774728182603464577139357067433
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:5fe2e616-4f60-4a88-93a2-a31fb0e1762b
1.spi_device_cfg_cmd.45319243927289762681855809117442789219201543766390963672860126647788030640650
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
Job ID: smart:8c05fac8-cb35-4c39-9aec-cbe253f1b8c0
... and 21 more failures.
0.spi_device_flash_all.34991522242356638345921077313445997201703343664120471943808958549020371822625
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:70d71d30-2bf7-4404-886f-e1918fe6d75b
1.spi_device_flash_all.44501438999131516636203186187940118995884926722904548933793194714071540181392
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:70ee6332-2ee6-4bde-9540-7c4865a62e07
... and 46 more failures.
0.spi_device_flash_and_tpm.13642169617353299505690122400768233613200392930560159192300802888493584693442
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:d4504765-aebd-4798-89cc-57cdcef517d9
1.spi_device_flash_and_tpm.63063579510453958050095599328936581420169570819286987208591893478706460450402
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:b7cc035c-56c8-403e-9601-a61c555581db
... and 40 more failures.
0.spi_device_flash_and_tpm_min_idle.63852446217595956794911871434573244079008864257558908587599410394185988205396
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:b141cdff-8f2b-410e-8646-7aa7fd5d32c9
1.spi_device_flash_and_tpm_min_idle.69434279015050980160825679560367367681802049246847297613634468802626641436394
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:eed639b3-faa1-415a-8568-cfcd5f51bd01
... and 43 more failures.
0.spi_device_stress_all.110087248976225372137576432573873212402850179076565353259224835928807344106670
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:b4b83ace-e6bd-4b60-809e-b000a64853e4
1.spi_device_stress_all.72860270876133745284173742420176071797985001326095766311506896422129099846179
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:adc4af11-1141-4633-9f7f-c00493fb22d9
... and 31 more failures.
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.42776645977628903638139708769973246176223590802473424321161791472692802845764
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 5037012 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[5])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 5037012 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 5037012 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[901])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.34248951283617815293074321166021477359368387331857138471987689165399092618566
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 6186452 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[0])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 6186452 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 6186452 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[896])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 20 failures:
Test spi_device_upload has 10 failures.
2.spi_device_upload.24119548974471118941395693318583361241144104406744118782593076207391536630104
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest/run.log
UVM_ERROR @ 119997655 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 225141869 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 225979215 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 1, test op = 0xa5
UVM_ERROR @ 1002139611 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1764011491 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
4.spi_device_upload.74812595101722305438978825340033217770089692553429363411433590321040116358569
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest/run.log
UVM_ERROR @ 19386400196 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 20712260196 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 20716516196 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 11, test op = 0xa0
UVM_INFO @ 22276420196 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 12, test op = 0x0
UVM_INFO @ 22456171196 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 13, test op = 0xbb
... and 8 more failures.
Test spi_device_flash_and_tpm has 4 failures.
3.spi_device_flash_and_tpm.11019242469764386857307997511924316372336903757732621492049703222324358510886
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 85652454 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 92958518 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 222906458 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 299018094 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 322224799 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
16.spi_device_flash_and_tpm.47155366346326915425015421911620905863180511652210722510019186082710269655929
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 8647575613 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 67522755870 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/11
UVM_FATAL @ 77017496607 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 77017496607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_flash_and_tpm_min_idle has 2 failures.
19.spi_device_flash_and_tpm_min_idle.107914600551665541486759182501561746987023573642613763846351262541124648557865
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 2893445802 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 6603864299 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h222118, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 6604697611 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h222118, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 6605530923 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h222118, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 6606364235 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h222118, wel:'h0, busy:'h0}} ) pred=0x0
22.spi_device_flash_and_tpm_min_idle.63272700717211738352071560393486683722029113896485546857362766995851339030530
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 1770045423 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x34449a) != exp '{'{other_status:'hd1126, wel:'h0, busy:'h0}, '{other_status:'hd1126, wel:'h0, busy:'h0}}
UVM_ERROR @ 1822305423 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x34449a) != exp '{'{other_status:'hd1126, wel:'h0, busy:'h0}, '{other_status:'hd1126, wel:'h0, busy:'h0}}
UVM_ERROR @ 2232795423 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x34449a) != exp '{'{other_status:'hd1126, wel:'h0, busy:'h0}, '{other_status:'hd1126, wel:'h0, busy:'h0}}
UVM_ERROR @ 3570885423 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x34449a) != exp '{'{other_status:'hd1126, wel:'h0, busy:'h0}, '{other_status:'hd1126, wel:'h0, busy:'h0}}
UVM_INFO @ 4389534423 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/2
Test spi_device_cfg_cmd has 4 failures.
32.spi_device_cfg_cmd.101945229284464458086505059689805985791116437234569273131409344087958982170051
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 22937029 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 23707887 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x4
UVM_ERROR @ 24218320 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2041a0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'hc2098, wel:'h0, busy:'h0}}
UVM_ERROR @ 24291239 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2041a0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'hc2098, wel:'h0, busy:'h0}}
UVM_ERROR @ 24374575 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2041a0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'hc2098, wel:'h0, busy:'h0}}
33.spi_device_cfg_cmd.19780188374657723052574903131148680779522697808303779006846662972664557130696
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 83659618 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 84826294 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 85201297 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 85576300 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 86409640 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x6
... and 2 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 15 failures:
Test spi_device_stress_all has 4 failures.
4.spi_device_stress_all.39961939869237945866480768723777311579715286691451406330859624763586516536153
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest/run.log
UVM_FATAL @ 343538509 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 343538509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_device_stress_all.53709157776267274560560599415457878081464818404613631213185553518561355016260
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest/run.log
UVM_FATAL @ 281862581 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 281862581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_flash_and_tpm has 4 failures.
6.spi_device_flash_and_tpm.80482100608606686747584466985264741648475280376344945242335144938630202039151
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 686215316 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 686215316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_device_flash_and_tpm.15925274058686701061661034231881232087423764735296586256499148873733937101188
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 610459759 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 610459759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_flash_and_tpm_min_idle has 3 failures.
8.spi_device_flash_and_tpm_min_idle.97439464398384237542144173622582683604905647585405432011626681033531748422006
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 207308291 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 207308291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_device_flash_and_tpm_min_idle.58239344217256240195925059392943682527295764325695296115091454813454221875501
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 34946940 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 34946940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_device_flash_all has 2 failures.
12.spi_device_flash_all.2247772266833388114250534461705242809530658891240325868203037987856882060513
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest/run.log
UVM_FATAL @ 74425373 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 74425373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.spi_device_flash_all.73446079232830691513506023810154551650375289423772182981014991495748138082482
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest/run.log
UVM_FATAL @ 589807298 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 589807298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_upload has 2 failures.
33.spi_device_upload.36853146288024179508079132741543784036448707372357637340322462381970505816130
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest/run.log
UVM_FATAL @ 938532764 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 938532764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.spi_device_upload.85152339178331040068278934970081494251489171613074008581525782561142007247867
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest/run.log
UVM_FATAL @ 121730593 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 121730593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 2 failures:
Test spi_device_stress_all has 1 failures.
33.spi_device_stress_all.21186709373491416459921258636790827858017822553009688429906645013115542350783
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest/run.log
UVM_ERROR @ 188833569 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h89dcf, wel:'h0, busy:'h0}}
UVM_ERROR @ 739162803 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 739570963 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 739979123 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 740387283 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
Test spi_device_cfg_cmd has 1 failures.
36.spi_device_cfg_cmd.48706443585448174045420354986388788909180369971721410275506747550933968929968
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 21491093 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x26d8ae) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h9b62b, wel:'h0, busy:'h0}, '{other_status:'h9b62b, wel:'h0, busy:'h0}}
UVM_INFO @ 21636931 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xb7
UVM_ERROR @ 21793186 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x26d8ae) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h9b62b, wel:'h0, busy:'h0}, '{other_status:'h9b62b, wel:'h0, busy:'h0}}
UVM_ERROR @ 21970275 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x26d8ae) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h9b62b, wel:'h0, busy:'h0}, '{other_status:'h9b62b, wel:'h0, busy:'h0}}
UVM_ERROR @ 22084862 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x26d8ae) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h9b62b, wel:'h0, busy:'h0}, '{other_status:'h9b62b, wel:'h0, busy:'h0}}
UVM_FATAL (spi_device_scoreboard.sv:1124) [scoreboard] timeout occurred! has 1 failures:
43.spi_device_flash_mode.102450770611498558830252263370253419240005549813739005015507423235035670664876
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest/run.log
UVM_FATAL @ 44419416822 ps: (spi_device_scoreboard.sv:1124) [uvm_test_top.env.scoreboard] timeout occurred!
UVM_INFO @ 44419416822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---