SPI_DEVICE/1R1W Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.659m	65.616ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	326.871us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.840s	119.696us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.120s	6.944ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.720s	805.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.040s	431.875us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.840s	119.696us	20	20	100.00
		spi_device_csr_aliasing	14.720s	805.939us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	12.874us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.310s	75.199us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.830s	104.597us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	3.492us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	33.916us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.770s	267.891us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.770s	267.891us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.390s	9.186ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	251.903us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.020s	21.154ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.920s	7.187ms	50	50	100.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	32.250s	110.759ms	50	50	100.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	32.250s	110.759ms	50	50	100.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.900s	5.348ms	49	50	98.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.900s	5.348ms	49	50	98.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.900s	5.348ms	49	50	98.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.900s	5.348ms	49	50	98.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.900s	5.348ms	49	50	98.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.330s	13.063ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.174m	28.235ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.174m	28.235ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.174m	28.235ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	47.980s	4.377ms	50	50	100.00
		spi_device_read_buffer_direct	20.760s	6.521ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.174m	28.235ms	50	50	100.00
		spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.904m	56.606ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.250s	3.890ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.250s	3.890ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.659m	65.616ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.486m	71.606ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.449m	887.015ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.760s	14.092us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	68.803us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.810s	418.502us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.810s	418.502us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	326.871us	5	5	100.00
		spi_device_csr_rw	2.840s	119.696us	20	20	100.00
		spi_device_csr_aliasing	14.720s	805.939us	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	846.215us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	326.871us	5	5	100.00
		spi_device_csr_rw	2.840s	119.696us	20	20	100.00
		spi_device_csr_aliasing	14.720s	805.939us	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	846.215us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.160s	155.229us	5	5	100.00
		spi_device_tl_intg_err	22.880s	814.735us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.880s	814.735us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.097m	70.985ms	49	50	98.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.21	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.31696637001551938718588633504268239437502310761166064069603108256922547493423
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1255334 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[88])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1255334 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1255334 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[984])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.32328387079509257793540098504934321093038504070510037993668698575212688086708
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   6061245 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[109])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   6061245 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   6061245 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1005])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1684) scoreboard [scoreboard] STATUS#* other bits mismatch: {pred (*) pred_fuzzy_q ('{}) , act (*)} has 1 failures:

Test spi_device_intercept has 1 failures.

11.spi_device_intercept.25010092367325651443890499647295249809564917335884446524549206849995398924076
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest/run.log

  UVM_ERROR @  92136204 ps: (spi_device_scoreboard.sv:1684) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] STATUS#1 other bits mismatch: {pred (0xf) pred_fuzzy_q ('{}) , act (0x2c)}
  UVM_INFO @ 361577062 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intercept_vseq] running iteration 3, test op = 0xb
  UVM_INFO @ 899331703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 41.spi_device_flash_mode_ignore_cmds.34083786848940840966099015044852031550903022124404290395582827156148499820538
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:860e9e71-777d-4ab1-932d-17a8336fadff
```