SPI_DEVICE/1R1W Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.882m	68.505ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.280s	42.053us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.660s	215.889us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.810s	5.893ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.870s	11.333ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.840s	223.283us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.660s	215.889us	20	20	100.00
		spi_device_csr_aliasing	23.870s	11.333ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	13.898us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.220s	144.674us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	24.453us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	1.453us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	15.628us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.240s	383.525us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.240s	383.525us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.430s	35.795ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	615.470us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	39.650s	13.695ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.710s	41.938ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.430s	45.283ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.430s	45.283ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	37.350s	20.176ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	37.350s	20.176ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	37.350s	20.176ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	37.350s	20.176ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	37.350s	20.176ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	26.660s	38.318ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.541m	21.087ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.541m	21.087ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.541m	21.087ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	51.230s	3.389ms	50	50	100.00
		spi_device_read_buffer_direct	19.740s	1.912ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.541m	21.087ms	50	50	100.00
		spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.183m	51.087ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.170s	3.768ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.170s	3.768ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.882m	68.505ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.637m	391.676ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.146m	476.464ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	48.143us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	49.207us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.250s	138.386us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.250s	138.386us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.280s	42.053us	5	5	100.00
		spi_device_csr_rw	2.660s	215.889us	20	20	100.00
		spi_device_csr_aliasing	23.870s	11.333ms	5	5	100.00
		spi_device_same_csr_outstanding	4.130s	174.718us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.280s	42.053us	5	5	100.00
		spi_device_csr_rw	2.660s	215.889us	20	20	100.00
		spi_device_csr_aliasing	23.870s	11.333ms	5	5	100.00
		spi_device_same_csr_outstanding	4.130s	174.718us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.070s	124.454us	5	5	100.00
		spi_device_tl_intg_err	23.650s	2.132ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.650s	2.132ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.272m	57.260ms	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.103317663557712624238394886543731698760792201664406836745640702739323946081817
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1493183 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[33])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1493183 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1493183 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[929])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.62804498750985733319934339371843814046710466055028988014068413740207852373737
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2473069 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[94])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2473069 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2473069 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[990])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

35.spi_device_flash_mode_ignore_cmds.97473304499779932772346286321270475158203000114861622482681583242062984173215
Line 273, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 15168494832 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0x6d7af4
  tl_ul_fuzzy_flash_status_q[i] = 0x6d7af4
  tl_ul_fuzzy_flash_status_q[i] = 0x63d48c
  UVM_INFO @ 16588165573 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 5/13