SPI_DEVICE/1R1W Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.492m	124.548ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.250s	35.878us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.740s	439.136us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.040s	1.491ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.170s	1.145ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.200s	326.114us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.740s	439.136us	20	20	100.00
		spi_device_csr_aliasing	23.170s	1.145ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	34.856us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.190s	26.598us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	35.581us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.800s	1.518us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	31.057us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.190s	1.100ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.190s	1.100ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.550s	9.342ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	150.302us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	35.400s	12.550ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.040s	16.309ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.440s	15.183ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.440s	15.183ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	47.120s	19.295ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	47.120s	19.295ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	47.120s	19.295ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	47.120s	19.295ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	47.120s	19.295ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	39.610s	12.611ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.057m	73.190ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.057m	73.190ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.057m	73.190ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.220m	16.659ms	50	50	100.00
		spi_device_read_buffer_direct	20.800s	3.199ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.057m	73.190ms	50	50	100.00
		spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.035m	266.981ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	18.440s	2.050ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	18.440s	2.050ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.492m	124.548ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.807m	626.845ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.097m	268.874ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	21.549us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	32.311us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.100s	70.312us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.100s	70.312us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.250s	35.878us	5	5	100.00
		spi_device_csr_rw	2.740s	439.136us	20	20	100.00
		spi_device_csr_aliasing	23.170s	1.145ms	5	5	100.00
		spi_device_same_csr_outstanding	4.720s	2.237ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.250s	35.878us	5	5	100.00
		spi_device_csr_rw	2.740s	439.136us	20	20	100.00
		spi_device_csr_aliasing	23.170s	1.145ms	5	5	100.00
		spi_device_same_csr_outstanding	4.720s	2.237ms	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.220s	83.621us	5	5	100.00
		spi_device_tl_intg_err	22.970s	2.093ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.970s	2.093ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.25

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.50318686531557350518340591898603964978635034798151695602668564741100114705116
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1075066 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[3])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1075066 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1075066 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[899])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.21312682415679906631268113953451953050503977643016487299541223816044063182842
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    833932 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[27])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    833932 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    833932 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[923])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.