SPI_DEVICE/1R1W Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.666m	57.012ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.520s	45.404us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.850s	416.256us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.050s	2.183ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.090s	4.221ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.830s	1.378ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.850s	416.256us	20	20	100.00
		spi_device_csr_aliasing	25.090s	4.221ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	40.232us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.290s	71.308us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.890s	67.283us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	2.643us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	18.865us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.540s	527.685us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.540s	527.685us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.220s	62.099ms	50	50	100.00
		spi_device_tpm_sts_read	1.070s	106.267us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.760s	7.697ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	25.470s	9.586ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	43.450s	12.207ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	43.450s	12.207ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.670s	4.124ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.670s	4.124ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.670s	4.124ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.670s	4.124ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.670s	4.124ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.870s	12.183ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.107m	66.221ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.107m	66.221ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.107m	66.221ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	46.590s	2.877ms	50	50	100.00
		spi_device_read_buffer_direct	22.850s	2.258ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.107m	66.221ms	50	50	100.00
		spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.563m	61.045ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.050s	2.300ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.050s	2.300ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.666m	57.012ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.085m	289.194ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.778m	153.991ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	13.264us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	22.214us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.350s	200.899us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.350s	200.899us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.520s	45.404us	5	5	100.00
		spi_device_csr_rw	2.850s	416.256us	20	20	100.00
		spi_device_csr_aliasing	25.090s	4.221ms	5	5	100.00
		spi_device_same_csr_outstanding	4.230s	63.803us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.520s	45.404us	5	5	100.00
		spi_device_csr_rw	2.850s	416.256us	20	20	100.00
		spi_device_csr_aliasing	25.090s	4.221ms	5	5	100.00
		spi_device_same_csr_outstanding	4.230s	63.803us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.290s	146.675us	5	5	100.00
		spi_device_tl_intg_err	18.950s	301.962us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.950s	301.962us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.373m	1.164s	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	94.01	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.1955992006502610589368595342343778418960537729700510882110397254084097020940
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2413499 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[60])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2413499 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2413499 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[956])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.42932576496822038634355947967206009777710576989437383566475469262013332147799
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3075535 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[51])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3075535 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3075535 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[947])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 39.spi_device_flash_mode_ignore_cmds.88851595904362116130623403430715627581422309561412986015136722580417053906002
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:576d23f4-42e4-49fc-8eaa-284631aa95f4
```