SPI_DEVICE/1R1W Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.228m	991.699ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.390s	177.870us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	229.584us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.800s	8.175ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.700s	4.962ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.820s	53.065us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	229.584us	20	20	100.00
		spi_device_csr_aliasing	25.700s	4.962ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.750s	11.248us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.950s	53.500us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.910s	21.586us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	7.059us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	15.533us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.550s	2.870ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.550s	2.870ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.340s	33.029ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	118.790us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.860s	68.853ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.430s	24.629ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.580s	57.310ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.580s	57.310ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.480s	10.631ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.480s	10.631ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.480s	10.631ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.480s	10.631ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.480s	10.631ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	41.070s	54.668ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.361m	40.278ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.361m	40.278ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.361m	40.278ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.064m	5.682ms	50	50	100.00
		spi_device_read_buffer_direct	20.620s	6.911ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.361m	40.278ms	50	50	100.00
		spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.443m	81.302ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.770s	8.753ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	33.770s	8.753ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.228m	991.699ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.947m	107.076ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.177m	116.127ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	12.915us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	31.606us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.610s	1.867ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.610s	1.867ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.390s	177.870us	5	5	100.00
		spi_device_csr_rw	2.860s	229.584us	20	20	100.00
		spi_device_csr_aliasing	25.700s	4.962ms	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	819.270us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.390s	177.870us	5	5	100.00
		spi_device_csr_rw	2.860s	229.584us	20	20	100.00
		spi_device_csr_aliasing	25.700s	4.962ms	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	819.270us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.270s	181.628us	5	5	100.00
		spi_device_tl_intg_err	25.960s	907.412us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.960s	907.412us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.826m	176.145ms	49	50	98.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.42762050436826116338917769177396803472396768520741446858069529604191192697714
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2513683 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[105])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2513683 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2513683 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1001])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.30715089794035380027390635265434052990371364003718014427845892890453948453893
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3701989 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[96])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3701989 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3701989 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[992])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:2235) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

23.spi_device_cfg_cmd.28992517101239505721149636070024624713903624029634390519924459714221608136392
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 883256612 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x84232e) != exp '{'{other_status:'h13d07a, wel:'h1, busy:'h0}, '{other_status:'h13d07a, wel:'h1, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}, '{other_status:'h10dd42, wel:'h0, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}}
  UVM_ERROR @ 883418228 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x84232e) != exp '{'{other_status:'h13d07a, wel:'h1, busy:'h0}, '{other_status:'h13d07a, wel:'h1, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}, '{other_status:'h10dd42, wel:'h0, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}}
  UVM_INFO @ 1132367474 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 9, test op = 0xe9
  UVM_ERROR @ 1132619999 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x84232e) != exp '{'{other_status:'h13d07a, wel:'h1, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}, '{other_status:'h1a00d9, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1133054342 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x84232e) != exp '{'{other_status:'h13d07a, wel:'h1, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}, '{other_status:'h2108cb, wel:'h0, busy:'h0}, '{other_status:'h1a00d9, wel:'h0, busy:'h0}}

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 27.spi_device_flash_mode_ignore_cmds.26286296417753085403138335523901125351141008752663067350062647400191791652426
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:57adbb2b-dbf8-4df4-8e49-53c04b01f2f2
```