SPI_DEVICE/1R1W Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.221m	85.965ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	155.372us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.010s	406.234us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.970s	3.600ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.110s	1.169ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.070s	164.353us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.010s	406.234us	20	20	100.00
		spi_device_csr_aliasing	20.110s	1.169ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	15.708us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.050s	118.413us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	22.870us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.800s	2.730us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	18.593us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.630s	258.658us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.630s	258.658us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.640s	11.862ms	50	50	100.00
		spi_device_tpm_sts_read	1.160s	282.802us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.200s	34.791ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	29.310s	9.961ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.760s	37.522ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.760s	37.522ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.460s	6.493ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.460s	6.493ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.460s	6.493ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.460s	6.493ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.460s	6.493ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.390s	12.425ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.302m	86.961ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.302m	86.961ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.302m	86.961ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.143m	4.411ms	50	50	100.00
		spi_device_read_buffer_direct	17.830s	1.980ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.302m	86.961ms	50	50	100.00
		spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.560m	307.544ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.450s	9.846ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.450s	9.846ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.221m	85.965ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.043m	334.142ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.147m	404.007ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	61.830us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	27.594us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.610s	297.310us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.610s	297.310us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	155.372us	5	5	100.00
		spi_device_csr_rw	3.010s	406.234us	20	20	100.00
		spi_device_csr_aliasing	20.110s	1.169ms	5	5	100.00
		spi_device_same_csr_outstanding	4.240s	529.826us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	155.372us	5	5	100.00
		spi_device_csr_rw	3.010s	406.234us	20	20	100.00
		spi_device_csr_aliasing	20.110s	1.169ms	5	5	100.00
		spi_device_same_csr_outstanding	4.240s	529.826us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.170s	92.624us	5	5	100.00
		spi_device_tl_intg_err	22.790s	7.334ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.790s	7.334ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	34.846m	1.500s	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.86889530437968364092421940473622484901200323693478311920160865982716885505965
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4560771 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[97])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4560771 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4560771 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[993])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.41324971574855655637938242154557987969461947197991121171440365884634714061616
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1810430 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[38])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1810430 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1810430 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[934])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 37.spi_device_flash_mode_ignore_cmds.46751899326992269722456408298929791627380908751119916762161368831453384304126
    Line 286, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```