SPI_DEVICE/1R1W Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.703m	144.298ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	181.124us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.780s	598.766us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.990s	1.810ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.230s	929.979us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.880s	59.107us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.780s	598.766us	20	20	100.00
		spi_device_csr_aliasing	23.230s	929.979us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	47.110us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.240s	372.432us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	79.061us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	1.423us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	16.087us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.550s	1.082ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.550s	1.082ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.510s	9.820ms	50	50	100.00
		spi_device_tpm_sts_read	1.090s	116.455us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.350s	50.905ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.570s	40.476ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	53.010s	152.400ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	53.010s	152.400ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.010s	62.795ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.010s	62.795ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.010s	62.795ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.010s	62.795ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.010s	62.795ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.350s	8.255ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.611m	12.920ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.611m	12.920ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.611m	12.920ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.546m	13.291ms	50	50	100.00
		spi_device_read_buffer_direct	19.570s	29.440ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.611m	12.920ms	50	50	100.00
		spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.796m	69.094ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.940s	3.975ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.940s	3.975ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.703m	144.298ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.673m	158.988ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.867m	383.308ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	17.906us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	43.621us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.960s	687.189us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.960s	687.189us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	181.124us	5	5	100.00
		spi_device_csr_rw	2.780s	598.766us	20	20	100.00
		spi_device_csr_aliasing	23.230s	929.979us	5	5	100.00
		spi_device_same_csr_outstanding	4.460s	219.251us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	181.124us	5	5	100.00
		spi_device_csr_rw	2.780s	598.766us	20	20	100.00
		spi_device_csr_aliasing	23.230s	929.979us	5	5	100.00
		spi_device_same_csr_outstanding	4.460s	219.251us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.240s	89.157us	5	5	100.00
		spi_device_tl_intg_err	24.570s	13.832ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.570s	13.832ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.581m	58.307ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	94.01	98.62	89.36	97.21	95.45	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.19966349141697847683799811507629998252166699549281279474240416445764665294879
      Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2007913 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[71])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2007913 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2007913 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[967])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.69109882711372270238255718742502054161938261327351821220473639982458746830384
      Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  15295474 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[61])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  15295474 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  15295474 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[957])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

Past Results

• Latest
• 2024.07.03_02.01.55
• 2024.07.02_10.57.21
• 2024.07.02_04.26.52
• 2024.07.01_11.09.22
• 2024.06.30_11.25.10
• 2024.06.29_09.48.15
• 2024.06.28_12.04.55