SPI_DEVICE/1R1W Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.818m	88.706ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.540s	49.465us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.010s	227.223us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.640s	5.178ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.880s	1.510ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.200s	105.689us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.010s	227.223us	20	20	100.00
		spi_device_csr_aliasing	21.880s	1.510ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	13.424us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	232.048us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	21.264us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	910.831ns	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.830s	111.090us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.710s	481.611us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.710s	481.611us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.030s	15.761ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	104.876us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	41.600s	31.619ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.700s	22.314ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	28.890s	9.858ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	28.890s	9.858ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.460s	15.955ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.460s	15.955ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.460s	15.955ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.460s	15.955ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.460s	15.955ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	52.520s	17.283ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.382m	254.536ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.382m	254.536ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.382m	254.536ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	52.210s	12.195ms	50	50	100.00
		spi_device_read_buffer_direct	19.910s	2.533ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.382m	254.536ms	50	50	100.00
		spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.527m	284.947ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.680s	12.831ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.680s	12.831ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.818m	88.706ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.842m	329.604ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.989m	883.582ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	51.057us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.940s	13.237us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.840s	160.903us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.840s	160.903us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.540s	49.465us	5	5	100.00
		spi_device_csr_rw	3.010s	227.223us	20	20	100.00
		spi_device_csr_aliasing	21.880s	1.510ms	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	779.433us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.540s	49.465us	5	5	100.00
		spi_device_csr_rw	3.010s	227.223us	20	20	100.00
		spi_device_csr_aliasing	21.880s	1.510ms	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	779.433us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.210s	72.608us	5	5	100.00
		spi_device_tl_intg_err	23.880s	829.761us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.880s	829.761us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.493m	162.446ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.21	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.25501678637191736470155879833224772382714990702389184395797429522422107210990
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   6426235 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[25])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   6426235 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   6426235 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[921])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.51043649233808405445789908437450828729482616305518170870894198339868378732648
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1143595 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[102])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1143595 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1143595 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[998])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.