SPI_DEVICE/1R1W Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.381m	80.360ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.370s	43.063us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.830s	450.714us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.830s	10.809ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.350s	6.199ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.290s	109.154us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.830s	450.714us	20	20	100.00
		spi_device_csr_aliasing	22.350s	6.199ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	14.746us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.380s	135.655us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	33.188us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	5.938us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	22.965us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.960s	1.077ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.960s	1.077ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.250s	7.012ms	50	50	100.00
		spi_device_tpm_sts_read	1.090s	111.214us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	53.020s	26.437ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.560s	62.324ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.200s	12.636ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.200s	12.636ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.700s	3.033ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.700s	3.033ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.700s	3.033ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.700s	3.033ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.700s	3.033ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.640s	13.011ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.481m	49.062ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.481m	49.062ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.481m	49.062ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.115m	4.296ms	50	50	100.00
		spi_device_read_buffer_direct	19.700s	6.966ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.481m	49.062ms	50	50	100.00
		spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.886m	65.541ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.060s	8.093ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.060s	8.093ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.381m	80.360ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.033m	355.172ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.962m	122.601ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	53.995us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	21.309us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.120s	199.710us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.120s	199.710us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.370s	43.063us	5	5	100.00
		spi_device_csr_rw	2.830s	450.714us	20	20	100.00
		spi_device_csr_aliasing	22.350s	6.199ms	5	5	100.00
		spi_device_same_csr_outstanding	4.740s	655.787us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.370s	43.063us	5	5	100.00
		spi_device_csr_rw	2.830s	450.714us	20	20	100.00
		spi_device_csr_aliasing	22.350s	6.199ms	5	5	100.00
		spi_device_same_csr_outstanding	4.740s	655.787us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.090s	78.850us	5	5	100.00
		spi_device_tl_intg_err	18.570s	606.715us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.570s	606.715us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.214m	77.532ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	94.01	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.112826660313595824839298527556627105300577571720041977866491440912983144213168
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   6739522 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[70])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   6739522 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   6739522 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[966])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.12770147691927789129285154370586942213128456456705535886151585671475179862160
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2068589 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[79])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2068589 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2068589 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[975])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.