SPI_DEVICE/1R1W Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.012m	144.178ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.070s	39.929us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.800s	349.569us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.860s	537.504us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.870s	4.558ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.340s	60.981us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.800s	349.569us	20	20	100.00
		spi_device_csr_aliasing	24.870s	4.558ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.030s	11.488us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.060s	112.407us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.220s	42.504us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.090s	3.151us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.930s	18.663us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.400s	336.244us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.400s	336.244us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	42.550s	19.756ms	50	50	100.00
		spi_device_tpm_sts_read	1.660s	401.682us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	58.930s	16.367ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	55.770s	26.215ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.720s	31.850ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.720s	31.850ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	38.370s	9.460ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	38.370s	9.460ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	38.370s	9.460ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	38.370s	9.460ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	38.370s	9.460ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	54.140s	25.511ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.056m	59.793ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.056m	59.793ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.056m	59.793ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.244m	5.868ms	50	50	100.00
		spi_device_read_buffer_direct	20.100s	5.471ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.056m	59.793ms	50	50	100.00
		spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.492m	76.003ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.220s	3.126ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.220s	3.126ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.012m	144.178ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.852m	78.021ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.731m	183.703ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	14.781us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.170s	16.767us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.810s	192.862us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.810s	192.862us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.070s	39.929us	5	5	100.00
		spi_device_csr_rw	3.800s	349.569us	20	20	100.00
		spi_device_csr_aliasing	24.870s	4.558ms	5	5	100.00
		spi_device_same_csr_outstanding	6.220s	794.718us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.070s	39.929us	5	5	100.00
		spi_device_csr_rw	3.800s	349.569us	20	20	100.00
		spi_device_csr_aliasing	24.870s	4.558ms	5	5	100.00
		spi_device_same_csr_outstanding	6.220s	794.718us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.830s	97.734us	5	5	100.00
		spi_device_tl_intg_err	23.540s	4.665ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.540s	4.665ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	12.703m	390.959ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	94.01	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.111766257455511714785651876797300796859381333524367617965320913468069884647920
Line 63, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4122431 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[102])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4122431 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4122431 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[998])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.86402666928760562774039596793707209612594701105874564931515564088932899519594
Line 63, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   5276048 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[33])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   5276048 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   5276048 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[929])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.