SPI_DEVICE/2P Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 24.240s 9.502ms 0 50 0.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.450s 91.787us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.730s 147.288us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 27.510s 1.809ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 24.470s 2.449ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.930s 170.072us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.730s 147.288us 20 20 100.00
spi_device_csr_aliasing 24.470s 2.449ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.710s 10.696us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.440s 99.078us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 csb_read spi_device_csb_read 0.870s 22.205us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.110s 32.369us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.780s 77.860us 20 20 100.00
V2 tpm_read spi_device_tpm_rw 11.130s 3.233ms 50 50 100.00
V2 tpm_write spi_device_tpm_rw 11.130s 3.233ms 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 26.170s 30.950ms 50 50 100.00
spi_device_tpm_sts_read 1.160s 137.230us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.330m 15.840ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 33.240s 66.276ms 50 50 100.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 55.870s 74.314ms 50 50 100.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 55.870s 74.314ms 50 50 100.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 cmd_info_slots spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 cmd_read_status spi_device_intercept 39.550s 19.167ms 44 50 88.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 cmd_read_jedec spi_device_intercept 39.550s 19.167ms 44 50 88.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 cmd_read_sfdp spi_device_intercept 39.550s 19.167ms 44 50 88.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 cmd_fast_read spi_device_intercept 39.550s 19.167ms 44 50 88.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 cmd_read_pipeline spi_device_intercept 39.550s 19.167ms 44 50 88.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 flash_cmd_upload spi_device_upload 51.210s 41.901ms 38 50 76.00
V2 mailbox_command spi_device_mailbox 3.058m 99.149ms 46 50 92.00
V2 mailbox_cross_outside_command spi_device_mailbox 3.058m 99.149ms 46 50 92.00
V2 mailbox_cross_inside_command spi_device_mailbox 3.058m 99.149ms 46 50 92.00
V2 cmd_read_buffer spi_device_flash_mode 1.860m 8.663ms 47 50 94.00
spi_device_read_buffer_direct 27.550s 10.860ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 3.058m 99.149ms 46 50 92.00
spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 quad_spi spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 dual_spi spi_device_flash_all 24.030s 2.716ms 0 50 0.00
V2 4b_3b_feature spi_device_cfg_cmd 20.530s 6.978ms 24 50 48.00
V2 write_enable_disable spi_device_cfg_cmd 20.530s 6.978ms 24 50 48.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 24.240s 9.502ms 0 50 0.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 45.100s 3.292ms 1 50 2.00
V2 stress_all spi_device_stress_all 1.619m 26.178ms 12 50 24.00
V2 alert_test spi_device_alert_test 0.780s 13.424us 50 50 100.00
V2 intr_test spi_device_intr_test 0.840s 15.470us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.740s 747.572us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.740s 747.572us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.450s 91.787us 5 5 100.00
spi_device_csr_rw 2.730s 147.288us 20 20 100.00
spi_device_csr_aliasing 24.470s 2.449ms 5 5 100.00
spi_device_same_csr_outstanding 4.130s 692.488us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.450s 91.787us 5 5 100.00
spi_device_csr_rw 2.730s 147.288us 20 20 100.00
spi_device_csr_aliasing 24.470s 2.449ms 5 5 100.00
spi_device_same_csr_outstanding 4.130s 692.488us 20 20 100.00
V2 TOTAL 792 980 80.82
V2S tl_intg_err spi_device_sec_cm 1.340s 84.939us 5 5 100.00
spi_device_tl_intg_err 23.670s 2.172ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 23.670s 2.172ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 882 1120 78.75

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 22 22 14 63.64
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.14 97.56 92.92 98.61 80.85 95.95 90.92 88.18

Failure Buckets

Past Results