e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 10.283m | 53.263ms | 47 | 50 | 94.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 22.111us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 5.000s | 37.704us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 186.711us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 4.000s | 36.889us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 31.952us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 5.000s | 37.704us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 4.000s | 36.889us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 3.000s | 106.623us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 5.000s | 56.344us | 5 | 5 | 100.00 |
V1 | TOTAL | 112 | 115 | 97.39 | |||
V2 | performance | spi_host_performance | 4.000s | 94.493us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 3.400m | 4.456ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 4.000s | 20.150us | 50 | 50 | 100.00 | ||
spi_host_event | 27.567m | 39.383ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 5.933m | 30.977ms | 50 | 50 | 100.00 |
V2 | speed | spi_host_speed | 5.933m | 30.977ms | 50 | 50 | 100.00 |
V2 | chip_select_timing | spi_host_speed | 5.933m | 30.977ms | 50 | 50 | 100.00 |
V2 | sw_reset | spi_host_sw_reset | 7.383m | 10.001ms | 44 | 50 | 88.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 154.937us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 5.933m | 30.977ms | 50 | 50 | 100.00 |
V2 | full_cycle | spi_host_speed | 5.933m | 30.977ms | 50 | 50 | 100.00 |
V2 | duplex | spi_host_smoke | 10.283m | 53.263ms | 47 | 50 | 94.00 |
V2 | tx_rx_only | spi_host_smoke | 10.283m | 53.263ms | 47 | 50 | 94.00 |
V2 | stress_all | spi_host_stress_all | 2.450m | 6.553ms | 49 | 50 | 98.00 |
V2 | spien | spi_host_spien | 6.183m | 8.733ms | 50 | 50 | 100.00 |
V2 | stall | spi_host_status_stall | 12.167m | 70.665ms | 47 | 50 | 94.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 1.100m | 1.483ms | 49 | 50 | 98.00 |
V2 | alert_test | spi_host_alert_test | 5.000s | 54.984us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 4.000s | 61.130us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 7.000s | 148.558us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 7.000s | 148.558us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 22.111us | 5 | 5 | 100.00 |
spi_host_csr_rw | 5.000s | 37.704us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 4.000s | 36.889us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 46.281us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 22.111us | 5 | 5 | 100.00 |
spi_host_csr_rw | 5.000s | 37.704us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 4.000s | 36.889us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 46.281us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 679 | 690 | 98.41 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 534.574us | 20 | 20 | 100.00 |
spi_host_sec_cm | 3.000s | 40.723us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 534.574us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 816 | 830 | 98.31 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 15 | 15 | 11 | 73.33 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.07 | 98.19 | 95.98 | 99.74 | 96.16 | 95.70 | 100.00 | 98.60 | 91.29 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 4 failures:
14.spi_host_sw_reset.204959706
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10141273794 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe7ac6314) == 0x0
UVM_INFO @ 10141273794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_sw_reset.2580775684
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10361194809 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf983a614) == 0x0
UVM_INFO @ 10361194809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 3 failures:
Test spi_host_stress_all has 1 failures.
11.spi_host_stress_all.797029804
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_stress_all/latest/run.log
UVM_FATAL @ 14055466393 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xdc1e7694) == 0x0
UVM_INFO @ 14055466393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 2 failures.
13.spi_host_smoke.258738298
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_smoke/latest/run.log
UVM_FATAL @ 77244574237 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb5d93494) == 0x0
UVM_INFO @ 77244574237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_smoke.181978669
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_smoke/latest/run.log
UVM_FATAL @ 178068129619 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6b0ff094) == 0x0
UVM_INFO @ 178068129619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 2 failures:
10.spi_host_sw_reset.2664308673
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10000688548 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xba2edcd4) == 0x0
UVM_INFO @ 10000688548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_sw_reset.3781548225
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001113443 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5a4540d4) == 0x0
UVM_INFO @ 10001113443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 2 failures:
18.spi_host_status_stall.811592891
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_status_stall.691333750
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 2 failures:
Test spi_host_idlecsbactive has 1 failures.
23.spi_host_idlecsbactive.4071750312
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10073557392 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x31ba2414) == 0x0
UVM_INFO @ 10073557392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
35.spi_host_smoke.2514988271
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_smoke/latest/run.log
UVM_FATAL @ 183782053304 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x18508f94) == 0x0
UVM_INFO @ 183782053304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
36.spi_host_status_stall.1099217362
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---