SPI_HOST Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.633m	13.108ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	18.021us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	17.612us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	2.435ms	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	28.064us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	90.931us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	17.612us	20	20	100.00
		spi_host_csr_aliasing	3.000s	28.064us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.048us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	37.975us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	4.000s	31.556us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.850m	38.456ms	47	50	94.00
		spi_host_error_cmd	3.000s	17.991us	50	50	100.00
		spi_host_event	22.367m	33.159ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.983m	28.794ms	50	50	100.00
V2	speed	spi_host_speed	5.983m	28.794ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.983m	28.794ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.683m	16.080ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	274.624us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.983m	28.794ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.983m	28.794ms	50	50	100.00
V2	duplex	spi_host_smoke	9.633m	13.108ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	9.633m	13.108ms	49	50	98.00
V2	stress_all	spi_host_stress_all	4.033m	23.114ms	50	50	100.00
V2	spien	spi_host_spien	6.967m	8.849ms	50	50	100.00
V2	stall	spi_host_status_stall	8.517m	11.680ms	43	50	86.00
V2	Idlecsbactive	spi_host_idlecsbactive	43.000s	3.045ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	16.490us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	42.010us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	118.851us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	118.851us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	18.021us	5	5	100.00
		spi_host_csr_rw	2.000s	17.612us	20	20	100.00
		spi_host_csr_aliasing	3.000s	28.064us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	55.050us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	18.021us	5	5	100.00
		spi_host_csr_rw	2.000s	17.612us	20	20	100.00
		spi_host_csr_aliasing	3.000s	28.064us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	55.050us	20	20	100.00
V2		TOTAL			680	690	98.55
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	83.029us	20	20	100.00
		spi_host_sec_cm	3.000s	68.415us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	83.029us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			819	830	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.05	98.13	95.98	99.73	96.52	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 5 failures:
- Test spi_host_status_stall has 5 failures.
  - 0.spi_host_status_stall.86045829633782519602294939060394794751587725647939655615351347565183721867145
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 20868036085 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x27b3e6d4) == 0x1
  UVM_INFO @ 20868036085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.spi_host_status_stall.64545201493280696597596406691400965842614884933564087051859040981877596670474
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 32177017149 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xaaeb6214) == 0x1
  UVM_INFO @ 32177017149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
- Test spi_host_overflow_underflow has 2 failures.
  - 2.spi_host_overflow_underflow.12201948855923796560699880836673438259912580619548340510466256709576082519381
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 42679861849 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x79063a14) == 0x0
  UVM_INFO @ 42679861849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.spi_host_overflow_underflow.52613869054056380426372045678309968277179962145667814121045721411153758151795
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 38456371516 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4900bf14) == 0x0
  UVM_INFO @ 38456371516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 2 failures.
  - 16.spi_host_status_stall.67991694839695261477242615763008127349638186570219343785123632429016687504359
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 77411258858 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe0f53a94) == 0x0
  UVM_INFO @ 77411258858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.spi_host_status_stall.14029949831729316026893762245678268020852365524988579685042170973134430524060
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 94858199360 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd92278d4) == 0x0
  UVM_INFO @ 94858199360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 1 failures.
  - 49.spi_host_smoke.51274602888062411323808838422089122467033637484470869624655018615244485135911
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 94255248200 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1e5c9414) == 0x0
  UVM_INFO @ 94255248200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_overflow_underflow has 1 failures.
  - 18.spi_host_overflow_underflow.104312658121423751052599505225225503783437309901845851931462726234873975526430
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 50576814674 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9c650714) == 0x0
  UVM_INFO @ 50576814674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8faf04697a`