SRAM_CTRL/MAIN Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.496m	925.295us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	43.143us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	12.753us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.840s	44.226us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	21.432us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.530s	4.365ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	12.753us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	21.432us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.086m	298.321ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.909m	8.747ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	31.205m	66.335ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.811m	80.138ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.044m	662.010ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.669m	67.800ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.043m	121.762ms	45	50	90.00
V2	executable	sram_ctrl_executable	40.411m	289.116ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.929m	1.337ms	49	50	98.00
		sram_ctrl_partial_access_b2b	8.901m	98.209ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.400m	1.612ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.859m	819.044us	50	50	100.00
V2	regwen	sram_ctrl_regwen	35.061m	17.410ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.990s	2.392ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.356h	733.077ms	42	50	84.00
V2	alert_test	sram_ctrl_alert_test	0.700s	25.969us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.540s	131.755us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.540s	131.755us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	43.143us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	12.753us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	21.432us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.770s	52.325us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	43.143us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	12.753us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	21.432us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.770s	52.325us	20	20	100.00
V2		TOTAL			722	740	97.57
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.240m	78.339ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.290s	653.346us	5	5	100.00
		sram_ctrl_tl_intg_err	2.780s	364.434us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.290s	653.346us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.780s	364.434us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	35.061m	17.410ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	12.753us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	40.411m	289.116ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	40.411m	289.116ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	40.411m	289.116ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.043m	121.762ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.240m	78.339ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.496m	925.295us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.496m	925.295us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	40.411m	289.116ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.290s	653.346us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.043m	121.762ms	45	50	90.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.290s	653.346us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.290s	653.346us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.496m	925.295us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.290s	653.346us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.609m	2.462ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1022	1040	98.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	10	62.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.41	100.00	97.91	100.00	100.00	99.72	99.70	98.52

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:405) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 12 failures:

Test sram_ctrl_stress_all has 7 failures.

12.sram_ctrl_stress_all.10463492285264334254980526381443234639208417312760420552319402661951040097123
Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 58515704518 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 58515704518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.sram_ctrl_stress_all.16832568563473364387020994789856629314811947050042520798597986359216777235343
Line 360, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 24047040566 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 24047040566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test sram_ctrl_lc_escalation has 5 failures.

17.sram_ctrl_lc_escalation.53632216438631647130809934037272294986714212675703765498492496649341484671205
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 22946818834 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 22946818834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.sram_ctrl_lc_escalation.13539583229895604713280444054649760085104131187516563194746801248195551195374
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 88778820193 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 88778820193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 44.sram_ctrl_regwen.115164630835737447408243648970879403879061931494404382920050642875692787914196
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 38498963408 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xeb61639c
  UVM_INFO @ 38498963408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.sram_ctrl_regwen.29749566639118223125802209379545086467184181027206915900704194469249734809102
    Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 113501124241 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xd51388b0
  UVM_INFO @ 113501124241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_partial_access has 1 failures.
  - 5.sram_ctrl_partial_access.67420474922067259000523386915394024004110956736590421058388835407695013970193
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest/run.log
```
  UVM_FATAL @ 16647738553 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x97f38105
  UVM_INFO @ 16647738553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 34.sram_ctrl_stress_all.101298704174263384611516520983300272861778844601945684608023385936465809449952
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest/run.log
```
      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1299805814 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1299805814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 39.sram_ctrl_bijection.65262955286443743298001484481965916369814602284530116799669172300304012629251
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 49.sram_ctrl_executable.30031400892785398506006894654288965046592835985330391989067375806251904227558
    Line 304, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 162091392169 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xa2cd60f3
  UVM_INFO @ 162091392169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```