SRAM_CTRL/MAIN Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.947m 11.776ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.780s 26.178us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.760s 17.204us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.120s 485.558us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 66.009us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.910s 1.442ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.760s 17.204us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 66.009us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.173m 89.715ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.061m 23.513ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 39.730m 26.248ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 9.328m 104.249ms 50 50 100.00
V2 bijection sram_ctrl_bijection 48.019m 1.000s 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 38.847m 81.861ms 49 50 98.00
V2 lc_escalation sram_ctrl_lc_escalation 1.815m 136.323ms 50 50 100.00
V2 executable sram_ctrl_executable 29.293m 268.872ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.353m 5.935ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.665m 24.108ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.761m 3.190ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.680m 804.203us 50 50 100.00
V2 regwen sram_ctrl_regwen 32.790m 27.301ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 4.380s 3.743ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.216h 1.456s 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.720s 14.005us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.290s 170.715us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.290s 170.715us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.780s 26.178us 5 5 100.00
sram_ctrl_csr_rw 0.760s 17.204us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 66.009us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 133.478us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.780s 26.178us 5 5 100.00
sram_ctrl_csr_rw 0.760s 17.204us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 66.009us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 133.478us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.012m 28.277ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.040s 276.043us 5 5 100.00
sram_ctrl_tl_intg_err 2.720s 347.495us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.040s 276.043us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.720s 347.495us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 32.790m 27.301ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.760s 17.204us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 29.293m 268.872ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 29.293m 268.872ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 29.293m 268.872ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.815m 136.323ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.012m 28.277ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.947m 11.776ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.947m 11.776ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.947m 11.776ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 29.293m 268.872ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.040s 276.043us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.815m 136.323ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.040s 276.043us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.040s 276.043us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.947m 11.776ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.040s 276.043us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.744m 11.956ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1035 1040 99.52

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 12 75.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results