de38ce313c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 3.050m | 19.434ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.710s | 53.904us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.690s | 27.358us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.160s | 246.427us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.720s | 30.106us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 4.330s | 1.422ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.690s | 27.358us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.720s | 30.106us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 6.209m | 79.608ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 3.067m | 6.512ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 203 | 205 | 99.02 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 29.775m | 113.628ms | 49 | 50 | 98.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 8.089m | 6.637ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 54.517m | 973.437ms | 50 | 50 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 30.053m | 80.626ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 2.067m | 126.447ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 29.727m | 117.228ms | 50 | 50 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.574m | 2.668ms | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 10.789m | 46.746ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.593m | 1.693ms | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.876m | 5.226ms | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 31.081m | 19.852ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 5.420s | 6.676ms | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 2.425h | 684.011ms | 49 | 50 | 98.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.800s | 42.284us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.350s | 140.305us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.350s | 140.305us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.710s | 53.904us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.690s | 27.358us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.720s | 30.106us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.860s | 213.698us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.710s | 53.904us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.690s | 27.358us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.720s | 30.106us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.860s | 213.698us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 738 | 740 | 99.73 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 59.820s | 25.190ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.500s | 407.920us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.630s | 365.872us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.500s | 407.920us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.630s | 365.872us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 31.081m | 19.852ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.690s | 27.358us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 29.727m | 117.228ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 29.727m | 117.228ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 29.727m | 117.228ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 2.067m | 126.447ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 59.820s | 25.190ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_smoke | 3.050m | 19.434ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 3.050m | 19.434ms | 48 | 50 | 96.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 3.050m | 19.434ms | 48 | 50 | 96.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 29.727m | 117.228ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.500s | 407.920us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 2.067m | 126.447ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.500s | 407.920us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.500s | 407.920us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 3.050m | 19.434ms | 48 | 50 | 96.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.500s | 407.920us | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 6.491m | 10.246ms | 49 | 50 | 98.00 |
| V3 | TOTAL | 49 | 50 | 98.00 | |||
| TOTAL | 1035 | 1040 | 99.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 14 | 87.50 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.97 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.44 |
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
21.sram_ctrl_smoke.65396833167126544423599150001990405528441551598413585504586428562998211848311
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest/run.log
UVM_FATAL @ 19433698654 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x4537ab3c
UVM_INFO @ 19433698654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.sram_ctrl_smoke.27343848624613621522751061713640066727861781772749022132230486478961601091876
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest/run.log
UVM_FATAL @ 14739925020 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x9dcd5769
UVM_INFO @ 14739925020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 1 failures:
9.sram_ctrl_stress_all.5329768496981425274971638226329856803629323532087996255972657597523394653102
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 2620076534 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 2620076534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
17.sram_ctrl_stress_all_with_rand_reset.20809879007994550729977857938149988961020842861083961316475676039250149348510
Line 303, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5844881396 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5844881396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
28.sram_ctrl_multiple_keys.97126128346793548070639785710096724302859913388621909366734614501184760201293
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest/run.log
UVM_FATAL @ 43114087789 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xce37fa1d
UVM_INFO @ 43114087789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---