SRAM_CTRL/MAIN Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.812m	1.287ms	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	62.410us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	19.245us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.440s	837.953us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	19.975us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.720s	740.752us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	19.245us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.975us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.015m	345.078ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.237m	35.988ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	41.934m	27.652ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.994m	5.545ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	51.829m	871.055ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	40.953m	21.329ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.119m	121.760ms	50	50	100.00
V2	executable	sram_ctrl_executable	44.446m	52.622ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.789m	5.307ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.544m	124.633ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.800m	1.554ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.809m	823.800us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.728m	32.052ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.150s	2.389ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.954h	289.783ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.760s	108.896us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.960s	1.797ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.960s	1.797ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	62.410us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	19.245us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.975us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	36.297us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	62.410us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	19.245us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.975us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	36.297us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.171m	70.490ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.460s	967.641us	5	5	100.00
		sram_ctrl_tl_intg_err	2.860s	1.798ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.460s	967.641us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.860s	1.798ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.728m	32.052ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	19.245us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	44.446m	52.622ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	44.446m	52.622ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	44.446m	52.622ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.119m	121.760ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.171m	70.490ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.812m	1.287ms	49	50	98.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.812m	1.287ms	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.812m	1.287ms	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	44.446m	52.622ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.460s	967.641us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.119m	121.760ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.460s	967.641us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.460s	967.641us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.812m	1.287ms	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.460s	967.641us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.171m	4.088ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 7.sram_ctrl_stress_all.95577358827751759590261109758724053651750794679752000318875728959873270797952
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:6dee47be-7552-4077-acb9-ff3c92a04863
```
  - 16.sram_ctrl_stress_all.60501458951151841589975685099972889066489836079908337574890726230478582341517
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:089c8dad-4fe0-4d67-ad3f-5d11f7989b26
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 2 failures.
  - 15.sram_ctrl_executable.63021479225357861173794178372263417139438860099555021167944283055832064688846
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 26721848433 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xa9d624ef
  UVM_INFO @ 26721848433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.sram_ctrl_executable.48988173977940018304301181736339987415339285119111481211278175935459495874690
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 58887423969 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x9c5f7fc0
  UVM_INFO @ 58887423969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_smoke has 1 failures.
  - 11.sram_ctrl_smoke.76657808975078014055799306181724127658349542823387363721516360056733732486472
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 21034191977 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe9ea6aeb
  UVM_INFO @ 21034191977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 41.sram_ctrl_bijection.110095325590934380439951787764952954925848070560965586077745333799716432468449
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8fdb25c8d9`