SRAM_CTRL/MAIN Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.883m	1.015ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	25.352us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	22.835us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.520s	403.717us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	20.740us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.370s	1.505ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	22.835us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.740us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.977m	94.067ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.875m	24.519ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	46.069m	126.343ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.136m	16.815ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.244m	689.760ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.985m	77.634ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.866m	146.753ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.956m	71.247ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.393m	2.208ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.270m	27.195ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.462m	795.946us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.071m	3.135ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	40.767m	85.075ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.410s	3.717ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.366h	196.444ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.740s	37.297us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.140s	195.196us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.140s	195.196us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	25.352us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	22.835us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.740us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	26.933us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	25.352us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	22.835us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.740us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	26.933us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.190s	117.224ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.290s	1.404ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.390s	1.515ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.290s	1.404ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.390s	1.515ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	40.767m	85.075ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	22.835us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.956m	71.247ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.956m	71.247ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.956m	71.247ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.866m	146.753ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.190s	117.224ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.883m	1.015ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.883m	1.015ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.883m	1.015ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.956m	71.247ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.290s	1.404ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.866m	146.753ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.290s	1.404ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.290s	1.404ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.883m	1.015ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.290s	1.404ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.583m	4.748ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	99.19	94.27	99.72	100.00	96.03	99.12	97.26

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 29.sram_ctrl_stress_all_with_rand_reset.47706792862114049942165975594868676134060125478570688538303356351055171717991
    Line 309, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2200393261 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2200393261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.sram_ctrl_stress_all_with_rand_reset.47918095076096459057621881636963977200824770600878203497231500500144792003941
    Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1092982901 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1092982901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 10.sram_ctrl_stress_all.29446398981196747968585551922764493641036160092302904713866716978290775721573
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:0735adda-90db-4bd4-afe0-f50bb78e1ca6
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 40.sram_ctrl_bijection.114473771192432576182691213222635788661398090155970067150164545469410681260748
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 48.sram_ctrl_executable.68307596085342376737407547550515381848503834711506749455016908686427978499675
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 38446365180 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xfb3b6f0e
  UVM_INFO @ 38446365180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 48.sram_ctrl_stress_all.29315911130188163471815858866972424518781544599162456975928785224449018413642
    Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 78463864213 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x998aaa7c
  UVM_INFO @ 78463864213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `25e609d6bb`