SRAM_CTRL/MAIN Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.709m	3.808ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	42.835us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.760s	13.261us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.350s	180.894us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.810s	67.433us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.840s	3.524ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.760s	13.261us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	67.433us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.317m	42.229ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.163m	24.126ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	38.287m	37.286ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.109m	120.549ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	47.808m	720.051ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.367m	48.267ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.391m	78.981ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.692m	18.519ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.629m	5.163ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.825m	99.766ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.775m	4.499ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.793m	3.394ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.278m	17.775ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.360s	6.675ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.440h	323.134ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.790s	39.873us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.090s	687.648us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.090s	687.648us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	42.835us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	13.261us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	67.433us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	48.684us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	42.835us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	13.261us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	67.433us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	48.684us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.000m	117.586ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.700s	1.686ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.740s	1.187ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.700s	1.686ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.740s	1.187ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.278m	17.775ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.760s	13.261us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.692m	18.519ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.692m	18.519ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.692m	18.519ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.391m	78.981ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.000m	117.586ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.709m	3.808ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.709m	3.808ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.709m	3.808ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.692m	18.519ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.700s	1.686ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.391m	78.981ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.700s	1.686ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.700s	1.686ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.709m	3.808ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.700s	1.686ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.063m	2.107ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 2.sram_ctrl_executable.51591502465521348013964493352118729622166094988327576320557307703595852231200
      Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 39802593169 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x579ce77
        UVM_INFO @ 39802593169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 12.sram_ctrl_multiple_keys.68794988333104741697590263792694392588506314642474027552785739934764687762633
      Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 87906036852 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xd846186d
        UVM_INFO @ 87906036852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 39.sram_ctrl_bijection.26872544364539618266002531576029296042131920542204903788551037046267274995181
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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