SRAM_CTRL/MAIN Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.438m 7.032ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 43.535us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 35.886us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.660s 2.088ms 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 24.000us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.610s 532.254us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 35.886us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 24.000us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.342m 82.708ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.200m 10.813ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 39.766m 49.758ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.876m 6.381ms 50 50 100.00
V2 bijection sram_ctrl_bijection 46.216m 165.284ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.425m 65.867ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.149m 62.233ms 50 50 100.00
V2 executable sram_ctrl_executable 31.073m 40.249ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.315m 8.468ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.216m 22.899ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.499m 1.533ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.839m 798.084us 50 50 100.00
V2 regwen sram_ctrl_regwen 28.241m 17.850ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.270s 6.706ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.727h 676.162ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.740s 16.570us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.770s 140.379us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.770s 140.379us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 43.535us 5 5 100.00
sram_ctrl_csr_rw 0.710s 35.886us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 24.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 94.191us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 43.535us 5 5 100.00
sram_ctrl_csr_rw 0.710s 35.886us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 24.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 94.191us 20 20 100.00
V2 TOTAL 738 740 99.73
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.333m 100.591ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 4.990s 5.081ms 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 8.520ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 4.990s 5.081ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 4.000s 8.520ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 28.241m 17.850ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 35.886us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 31.073m 40.249ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 31.073m 40.249ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 31.073m 40.249ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.149m 62.233ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.333m 100.591ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.438m 7.032ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.438m 7.032ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.438m 7.032ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 31.073m 40.249ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 4.990s 5.081ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.149m 62.233ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 4.990s 5.081ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 4.990s 5.081ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.438m 7.032ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 4.990s 5.081ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 5.147m 12.012ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results