SRAM_CTRL/MAIN Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.909m 453.357us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.830s 22.564us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.780s 146.918us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.320s 871.512us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.830s 17.011us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.650s 6.967ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.780s 146.918us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 17.011us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.024m 71.894ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.951m 54.848ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 32.643m 69.574ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.934m 6.434ms 50 50 100.00
V2 bijection sram_ctrl_bijection 49.803m 173.261ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 32.755m 71.661ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.977m 120.873ms 50 50 100.00
V2 executable sram_ctrl_executable 29.628m 92.782ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.611m 535.074us 50 50 100.00
sram_ctrl_partial_access_b2b 11.469m 88.784ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.577m 8.516ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.648m 3.884ms 50 50 100.00
V2 regwen sram_ctrl_regwen 26.221m 17.865ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.540s 6.726ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.716h 458.719ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.730s 13.274us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.590s 632.876us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.590s 632.876us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.830s 22.564us 5 5 100.00
sram_ctrl_csr_rw 0.780s 146.918us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 17.011us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.920s 30.384us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.830s 22.564us 5 5 100.00
sram_ctrl_csr_rw 0.780s 146.918us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 17.011us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.920s 30.384us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 57.320s 30.569ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.610s 429.604us 5 5 100.00
sram_ctrl_tl_intg_err 3.660s 657.994us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.610s 429.604us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.660s 657.994us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 26.221m 17.865ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.780s 146.918us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 29.628m 92.782ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 29.628m 92.782ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 29.628m 92.782ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.977m 120.873ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 57.320s 30.569ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.909m 453.357us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.909m 453.357us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.909m 453.357us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 29.628m 92.782ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.610s 429.604us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.977m 120.873ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.610s 429.604us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.610s 429.604us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.909m 453.357us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.610s 429.604us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.960m 5.425ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results