SRAM_CTRL/MAIN Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.671m	4.289ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	22.508us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.760s	26.607us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.100s	375.408us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	14.879us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.260s	4.908ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.760s	26.607us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	14.879us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.617m	360.029ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.246m	23.160ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.981m	97.140ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.998m	25.574ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.158m	167.004ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.712m	21.332ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.931m	60.543ms	50	50	100.00
V2	executable	sram_ctrl_executable	31.540m	13.092ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	3.119m	5.307ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.658m	91.974ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.840m	800.350us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.015m	9.780ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.861m	39.517ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.510s	6.719ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.785h	3.293s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.740s	25.570us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.020s	489.549us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.020s	489.549us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	22.508us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	26.607us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	14.879us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	27.120us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	22.508us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	26.607us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	14.879us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	27.120us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	56.770s	28.167ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.790s	629.537us	5	5	100.00
		sram_ctrl_tl_intg_err	3.050s	618.110us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.790s	629.537us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.050s	618.110us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.861m	39.517ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.760s	26.607us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.540m	13.092ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.540m	13.092ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.540m	13.092ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.931m	60.543ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	56.770s	28.167ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.671m	4.289ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.671m	4.289ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.671m	4.289ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.540m	13.092ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.790s	629.537us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.931m	60.543ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.790s	629.537us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.790s	629.537us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.671m	4.289ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.790s	629.537us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.026m	6.161ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.sram_ctrl_stress_all_with_rand_reset.104769134112341737852741912251586281063510862839623859588865482327228895366589
      Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2050387318 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2050387318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 43.sram_ctrl_bijection.65716437297829156562651935143209802525979803252249930143575302962578530263826
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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