SRAM_CTRL/MAIN Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.875m 793.662us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 16.254us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 53.561us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.870s 46.714us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 88.356us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.930s 1.428ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 53.561us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 88.356us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.517m 82.800ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.174m 25.211ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 40.611m 113.771ms 48 50 96.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.277m 48.488ms 50 50 100.00
V2 bijection sram_ctrl_bijection 48.451m 242.771ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 37.020m 19.311ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.092m 63.335ms 50 50 100.00
V2 executable sram_ctrl_executable 38.441m 26.691ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 3.320m 1.732ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.848m 25.528ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 3.044m 1.179ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.865m 842.741us 50 50 100.00
V2 regwen sram_ctrl_regwen 30.619m 58.504ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.480s 6.722ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.788h 192.784ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.720s 20.597us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.210s 518.325us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.210s 518.325us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 16.254us 5 5 100.00
sram_ctrl_csr_rw 0.710s 53.561us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 88.356us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 99.090us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 16.254us 5 5 100.00
sram_ctrl_csr_rw 0.710s 53.561us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 88.356us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 99.090us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 55.120s 29.396ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.180s 890.716us 5 5 100.00
sram_ctrl_tl_intg_err 4.430s 4.548ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.180s 890.716us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 4.430s 4.548ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 30.619m 58.504ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 53.561us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.441m 26.691ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.441m 26.691ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.441m 26.691ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.092m 63.335ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 55.120s 29.396ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.875m 793.662us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.875m 793.662us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.875m 793.662us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.441m 26.691ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.180s 890.716us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.092m 63.335ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.180s 890.716us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.180s 890.716us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.875m 793.662us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.180s 890.716us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.506m 2.721ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1035 1040 99.52

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 12 75.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results