SRAM_CTRL/MAIN Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 3.022m 1.095ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 17.856us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 29.132us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.070s 239.575us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.790s 35.594us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.620s 1.489ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 29.132us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 35.594us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.727m 179.492ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.133m 22.719ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 31.076m 112.015ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.759m 24.215ms 50 50 100.00
V2 bijection sram_ctrl_bijection 50.378m 172.399ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 37.657m 62.782ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.766m 59.663ms 50 50 100.00
V2 executable sram_ctrl_executable 46.362m 199.191ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.804m 3.316ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.087m 44.583ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.616m 1.596ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.843m 3.261ms 50 50 100.00
V2 regwen sram_ctrl_regwen 41.519m 46.745ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.360s 2.784ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.731h 467.751ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.730s 38.408us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.140s 148.749us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.140s 148.749us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 17.856us 5 5 100.00
sram_ctrl_csr_rw 0.720s 29.132us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 35.594us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 19.282us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 17.856us 5 5 100.00
sram_ctrl_csr_rw 0.720s 29.132us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 35.594us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 19.282us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.269m 87.836ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 2.770s 246.825us 5 5 100.00
sram_ctrl_tl_intg_err 2.530s 737.604us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 2.770s 246.825us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.530s 737.604us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 41.519m 46.745ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 29.132us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 46.362m 199.191ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 46.362m 199.191ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 46.362m 199.191ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.766m 59.663ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.269m 87.836ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 3.022m 1.095ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 3.022m 1.095ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 3.022m 1.095ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 46.362m 199.191ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 2.770s 246.825us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.766m 59.663ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 2.770s 246.825us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 2.770s 246.825us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 3.022m 1.095ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 2.770s 246.825us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.462m 3.189ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1036 1040 99.62

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results