SRAM_CTRL/MAIN Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.945m 1.294ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 129.894us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 21.552us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.830s 1.536ms 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 34.969us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 6.520s 5.899ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 21.552us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 34.969us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.204m 108.673ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.982m 26.528ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 37.645m 20.293ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.060m 25.909ms 50 50 100.00
V2 bijection sram_ctrl_bijection 48.865m 344.676ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 59.612m 18.125ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.312m 64.468ms 50 50 100.00
V2 executable sram_ctrl_executable 38.244m 26.657ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 3.138m 7.489ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.978m 117.975ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.781m 781.869us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.412m 807.227us 50 50 100.00
V2 regwen sram_ctrl_regwen 31.547m 16.044ms 47 50 94.00
V2 ram_cfg sram_ctrl_ram_cfg 4.410s 3.349ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.803h 1.453s 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.730s 17.522us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.490s 216.945us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.490s 216.945us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 129.894us 5 5 100.00
sram_ctrl_csr_rw 0.720s 21.552us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 34.969us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 75.796us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 129.894us 5 5 100.00
sram_ctrl_csr_rw 0.720s 21.552us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 34.969us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 75.796us 20 20 100.00
V2 TOTAL 732 740 98.92
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.004m 26.121ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.570s 583.808us 5 5 100.00
sram_ctrl_tl_intg_err 2.390s 190.122us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.570s 583.808us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.390s 190.122us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 31.547m 16.044ms 47 50 94.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 21.552us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.244m 26.657ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.244m 26.657ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.244m 26.657ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.312m 64.468ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.004m 26.121ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.945m 1.294ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.945m 1.294ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.945m 1.294ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.244m 26.657ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.570s 583.808us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.312m 64.468ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.570s 583.808us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.570s 583.808us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.945m 1.294ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.570s 583.808us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.334m 12.192ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1031 1040 99.13

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 12 75.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results