SRAM_CTRL/RET Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.557m	260.314us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	15.493us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.800s	117.471us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.980s	510.484us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	20.013us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.110s	65.790us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.800s	117.471us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	20.013us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.700s	9.353ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.740s	2.365ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.265m	186.902ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.513m	20.366ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.587m	57.716ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	26.843m	3.944ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.690s	1.299ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.063m	57.767ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.160m	1.832ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.086m	54.655ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.500m	137.797us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.309m	572.668us	50	50	100.00
V2	regwen	sram_ctrl_regwen	35.551m	200.000ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.200s	32.061us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.640h	21.651ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.700s	17.162us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.980s	522.871us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.980s	522.871us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	15.493us	5	5	100.00
		sram_ctrl_csr_rw	0.800s	117.471us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	20.013us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	70.717us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	15.493us	5	5	100.00
		sram_ctrl_csr_rw	0.800s	117.471us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	20.013us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	70.717us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.690s	398.696us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.350s	3.283ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.470s	258.347us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.350s	3.283ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.470s	258.347us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	35.551m	200.000ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.800s	117.471us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.063m	57.767ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.063m	57.767ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.063m	57.767ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.690s	1.299ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.690s	398.696us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.557m	260.314us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.557m	260.314us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.063m	57.767ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.350s	3.283ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.690s	1.299ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.350s	3.283ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.350s	3.283ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.557m	260.314us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.350s	3.283ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.740h	8.798ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test sram_ctrl_regwen has 1 failures.

29.sram_ctrl_regwen.4229799463
Line 317, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sram_ctrl_multiple_keys has 1 failures.

49.sram_ctrl_multiple_keys.446742107
Line 329, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 43.sram_ctrl_multiple_keys.3685734865
    Line 255, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 54247166209 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x992cd7bb
  UVM_INFO @ 54247166209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```